Semiconductor device equipped with a pull-down circuit
View Patent ↗Provided is a semiconductor device equipped with a pull-down circuit capable of reducing its area. The pull-down circuit is formed of a depletion type NMOS transistor in which a gate thereof is connected to a ground potential, and an enhancement type NMOS transistor in which a gate and a drain thereof are connected to a source of the depletion type NMOS transistor and a source thereof is connected to the ground potential. An overdrive voltage of the depletion type NMOS transistor is reduced by a threshold voltage of the enhancement type NMOS transistor, whereby a size of the depletion type NMOS transistor can be reduced. Accordingly, an area of the pull-down circuit can be reduced.
1. A semiconductor device comprising:
an internal node; and
a pull-down circuit connected to the internal node for fixing the internal node to low when a power signal is activated or a power supply voltage decreases, the pull-down circuit comprising:
an input terminal connected to the internal node;
a depletion type NMOS transistor connected to the input terminal; and
an enhancement type NMOS transistor comprising a gate and a drain connected to a source of the depletion type NMOS transistor, where an absolute value of a threshold voltage of the depletion type NMOS transistor is greater than an absolute value of a threshold voltage of the enhancement type NMOS transistor.
2. The semiconductor device of claim 1 , the depletion type NMOS transistor comprising:
a drain connected to the input terminal; and
a gate connected to a ground terminal.
3. The semiconductor device of claim 1 , the enhancement type NMOS transistor comprising a source connected to a ground terminal.
4. The semiconductor device of claim 1 , where the depletion type NMOS transistor is configured to have a greater driving performance than the enhancement type NMOS transistor.
5. The semiconductor device of claim 1 , the depletion type NMOS transistor comprising a width of approximately 5 μm and a length of approximately 1 μm.
6. The semiconductor device of claim 1 , the enhancement type NMOS transistor comprising a width of approximately 2 μm and a length of approximately 50 μm.
7. A semiconductor device comprising:
an internal node; and
a pull-down circuit connected to the internal node for fixing the internal node to low when a power signal is activated or a power supply voltage decreases, the pull-down circuit comprising:
a depletion type NMOS transistor comprising:
a drain connected to an internal node of the semiconductor device;
a gate connected to a ground terminal; and
a source; and
an enhancement type NMOS transistor comprising:
a gate and a drain connected to the source of the depletion type NMOS transistor; and
a source connected to the ground terminal.
8. The semiconductor device of claim 7 , where an absolute value of a threshold voltage of the depletion type NMOS transistor is greater than an absolute value of a threshold voltage of the enhancement type NMOS transistor.
9. The semiconductor device of claim 7 , the depletion type NMOS transistor comprising a width of approximately 5 μm and a length of approximately 1 μm.
10. The semiconductor device of claim 7 , the enhancement type NMOS transistor comprising a width of approximately 2 μm and a length of approximately 50 μm.
11. A semiconductor device comprising:
an internal node; and
a pull-down circuit connected to the internal node for fixing the internal node to low when a power signal is activated or a power supply voltage decreases, the pull-down circuit comprising:
a depletion type NMOS transistor connected to an internal node of the semiconductor device; and
an enhancement type NMOS transistor comprising a gate and a drain connected to a source of the depletion type NMOS transistor.
12. The semiconductor device of claim 11 , the depletion type NMOS transistor comprising:
a drain connected to the internal node; and
a gate connected to a ground terminal.
13. The semiconductor device of claim 11 , the enhancement type NMOS transistor comprising a source connected to a ground terminal.
14. The semiconductor device of claim 11 , where the depletion type NMOS transistor is configured to have a greater driving performance than the enhancement type NMOS transistor.
15. The semiconductor device of claim 11 , the depletion type NMOS transistor comprising a width of approximately 5 μm and a length of approximately 1 μm.
16. The semiconductor device of claim 11 , the enhancement type NMOS transistor comprising a width of approximately 2 μm and a length of approximately 50 μm.