Filler circuit cell
View Patent ↗A filler circuit cell is disclosed. The filler circuit cell includes a decoupled capacitor, a tie low circuit and a tie high circuit. The decoupled capacitor includes a first NMOS transistor and a first PMOS transistor, in which the source/drain of the first NMOS transistor is connected to a second voltage source and the source/drain of the first PMOS transistor is connected to a first voltage source. The tie low circuit includes a second NMOS transistor and a second PMOS transistor and the tie high circuit includes a third NMOS transistor and a third PMOS transistor.
1. A filler circuit cell, comprising:
a decoupled capacitor comprising a first n-type metal-oxide semiconductor (NMOS) transistor and a first p-type metal-oxide semiconductor (PMOS) transistor, wherein the source and drain of the first NMOS transistor is connected to a second voltage source and the source and drain of the first PMOS transistor is connected to a first voltage source;
a tie low circuit disposed between the first voltage source, a gate of the first PMOS transistor and the second voltage source, wherein the tie low circuit comprises a second NMOS transistor and a second PMOS transistor; and
a tie high circuit disposed between the first voltage source, a gate of the first NMOS transistor and the second voltage source, wherein the tie high circuit comprises a third NMOS transistor and a third PMOS transistor.
2. The filler circuit cell of claim 1 , wherein one source/drain of the second NMOS transistor is connected to the gate of the first PMOS transistor.
3. The filler circuit cell of claim 2 , wherein the other source and drain of the second NMOS transistor is connected to the second voltage source.
4. The filler circuit cell of claim 1 , wherein one source and drain and gate of the second PMOS transistor is connected to the gate of the second NMOS transistor.
5. The filler circuit cell of claim 4 , wherein the other source and drain of the second PMOS transistor is connected to the first voltage source.
6. The filler circuit cell of claim 1 , wherein one source and drain and gate of the third NMOS transistor is connected to the gate of the third PMOS transistor.
7. The filler circuit cell of claim 6 , wherein the other source and drain of the third NMOS transistor is connected to the second voltage source.
8. The filler circuit cell of claim 1 , wherein one source and drain of the third PMOS transistor is connected to the gate of the first NMOS transistor.
9. The filler circuit cell of claim 8 , wherein the other source and drain of the third PMOS transistor is connected to the first voltage source.
10. The filler circuit cell of claim 1 , wherein the first voltage source is a Vdd voltage source.
11. The filler circuit cell of claim 1 , wherein the second voltage source is a Vss voltage source.
12. A filler circuit cell, comprising:
a decoupled capacitor comprising a first MOS transistor, wherein the source and drain of the first MOS transistor is connected to a first voltage source; and
a voltage stabilizing unit disposed between the first voltage source, a gate of the first MOS transistor and a second voltage source to prevent damage for the gate of the first MOS transistor caused by sudden glitches, wherein the voltage stabilizing unit comprises a second MOS transistor and a third MOS transistor.
13. The filler circuit cell of claim 12 , wherein one source and drain of the second MOS transistor is connected to the gate of the first MOS transistor.
14. The filler circuit cell of claim 13 , wherein another source and drain of the second MOS transistor is connected to the second voltage source.
15. The filler circuit cell of claim 12 , wherein one source and drain of the third MOS transistor is connected to the first voltage source.
16. The filler circuit cell of claim 15 , wherein another source and drain and gate of the third MOS transistor is connected to the gate of the second MOS transistor.
17. The filler circuit cell of claim 12 , wherein the first voltage source is a Vdd voltage source.
18. The filler circuit cell of claim 14 , wherein the second voltage source is a Vss voltage source.
19. The filler circuit cell of claim 12 , wherein the first voltage source is a Vss voltage source.
20. The filler circuit cell of claim 14 , wherein the second voltage source is a Vdd voltage source.