In one embodiment, a method for trusted booting of a cryptographic processor system is disclosed. Default image(s) is loaded into a field-programmable logic chip or circuit (FPLC). The default image(s) cannot perform cryptographic processing, but can perform a first algorithm that is unclassified. A processor, internal or external to the FPLC, can be used with the default image. A multi-layer or multi-part key has portions stored in two different places. A protected image is decrypted with the multi-layer key using the first algorithm and loaded into the FPLC. Cryptographic processing is performed using a second algorithm classified by the government.
1. A method for booting with multi-layered security that cryptographically processes information, the method comprising:
loading a default image into a field-programmable logic chip (FPLC), wherein:
the default image prevents the FPLC from passing information from a first port to a second port,
the default image includes a first algorithm that is unclassified by the government, and
the default image allows operational software to function;
loading a multi-layered key, wherein:
a first layer of the multilayer key is stored separate from a second layer of the multilayer key, and
the first and second layers are used to formulate the multi-layer key;
decrypting a protected image using the multi-layered key and the first algorithm to produce a decrypted image, wherein the protected image is encrypted;
loading the decrypted image into the FPLC; and
performing cryptographic processing using the decrypted image and a second algorithm, which is classified by the government, wherein the cryptographic processing operates on information passing from the first port to the second port.
2. The method as recited in claim 1 , wherein the unclassified algorithm is software implemented.
3. The method as recited in claim 1 , wherein the operation software is run on a processor external to the FPLC.
4. The method as recited in claim 1 , wherein the unclassified algorithm is a soft core.
5. The method as recited in claim 1 , wherein the loading the default image is performed after decrypting the default image on-chip within the FPLC.
6. The method as recited in claim 1 , wherein the loading the multi-layer key includes loading the first and second layers of the multi-layered key from at least two different chips.
7. The method as recited in claim 1 , wherein the FPLC includes a plurality of FPGAs.
8. The method as recited in claim 1 , wherein the default image is isolated from the decrypted image within a single field-programmable gate array (FPGA).
9. A cryptographic processing system for booting a field-programmable logic chip (FPLC) with multi-layered keys, the cryptographic processing system comprising:
a first port for receiving information for cryptographic processing;
a second port for transmitting information after cryptographic processing;
a default image loaded in the FPLC, wherein:
the default image prevents the FPLC from passing information from a first port to a second port,
the default image includes a first algorithm that is unclassified by the government, and
the default image allows operational software to function;
a multi-layered key, wherein:
a first layer of the multilayer key is stored separate from a second layer of the multilayer key, and
the first and second layers are used to formulate the multi-layer key;
a protected image that is decrypted using the multi-layered key and the first algorithm to produce a decrypted image, wherein:
the decrypted image is loaded into the FPLC, and
cryptographic processing is performed using the decrypted image and a second algorithm, which is classified by the government, wherein the cryptographic processing operates on information passing from the first port to the second port.
10. The cryptographic processing system as recited in claim 9 , wherein the unclassified algorithm is software implemented.
11. The cryptographic processing system as recited in claim 9 , wherein the unclassified algorithm is a soft core.
12. The cryptographic processing system as recited in claim 9 , wherein the loading the default image is performed after decrypting the default image on-chip within the FPLC.
13. The cryptographic processing system as recited in claim 9 , wherein the loading the multi-layer key includes loading the first and second layers of the multi-layered key from at least two different chips.
14. The cryptographic processing system as recited in claim 9 , wherein the FPLC includes a plurality of FPGAs.
15. The cryptographic processing system as recited in claim 9 , wherein the default image is isolated from the decrypted image within a single field-programmable gate array (FPGA).
16. A cryptographic processing system for booting a field-programmable logic chip (FPLC) with multi-layered keys, the cryptographic processing system comprising:
first means for loading a default image into a field-programmable logic chip (FPLC), wherein:
the default image prevents the FPLC from passing information from a first port to a second port,
the default image includes a first algorithm that is unclassified by the government, and
the default image allows operational software to function;
second means for loading a multi-layered key, wherein:
a first layer of the multilayer key is stored separate from a second layer of the multilayer key, and
the first and second layers are used to formulate the multi-layer key;
means for decrypting a protected image using the multi-layered key and the first algorithm to produce a decrypted image;
third means for loading the decrypted image into the FPLC; and
means for cryptographically processing that uses the decrypted image and a second algorithm, which is classified by the government, wherein the cryptographic processing operates on information passing from the first port to the second port.
17. The cryptographic processing system as recited in claim 16 , wherein the unclassified algorithm is software implemented.
18. The cryptographic processing system as recited in claim 16 , wherein the unclassified algorithm is a soft core.
19. The cryptographic processing system as recited in claim 16 , wherein the loading the default image is performed after decrypting the default image on-chip within the FPLC.
20. The cryptographic processing system as recited in claim 16 , wherein the loading the multi-layer key includes loading the first and second layers of the multi-layered key from at least two different chips.
21. The cryptographic processing system as recited in claim 16 , wherein the FPLC includes a plurality of FPGAs.
22. The cryptographic processing system as recited in claim 16 , wherein the default image is isolated from the decrypted image within a single field-programmable gate array (FPGA).