Switching architecture with packet encapsulation
View Patent ↗The invention includes, among other things, a system for passing TDM traffic through a packet switch. In one embodiment, the system includes a packet switch that has a plurality of data ports and is capable of routing FSDU packets between the plurality of data ports. A TDM encapsulation circuit process a TDM data flow that is incoming to the switch. A circuit demultiplexer processes the incoming data flow to buffer data associated with different TDM circuits into different buffer locations. A timer monitors the amount of time available to fill the FSDU, and when the time period reaches the frame boundary, an FSDU generator generates an FSDU that is filled with data associated with the TDM circuits. Header information is added for allowing the packet switch to route the generated FSDU to a port associated with the respective TDM circuit.
1. A system for passing Time Division Multiplexed (TDM) traffic through a packet switch, comprising
a packet switch having a plurality of data ports and being capable of routing Fixed Size Data Unit (FSDU) packets between the plurality of data ports, the packet switch routing FSDU packets within the packet switch based on header information within respective FSDU packets;
a TDM encapsulation circuit coupled to a data flow of TDM data and having a circuit demultiplexer for processing an incoming data flow of TDM data to buffer data associated with different TDM circuits into different buffer locations,
a timer for monitoring a frame boundary,
a FSDU generator for generating an FSDU and filling the generated FSDU with data associated with a respective one of the TDM circuits and for generating the header information for allowing the packet switch to route the generated FSDU to a port associated with the respective one of the TDM circuits;
a bandwidth allocation process for allocating bandwidth for generated FSDU traffic to provide a predetermined latency period for routing FSDU traffic through the packet switch; and
a jitter buffer for receiving the generated FSDU traffic with the predetermined latency period, the jitter buffer further for reducing variable delays in the FSDU traffic, wherein the jitter buffer has a size selected as a function of a minimum and maximum latency of the FSDU traffic;
wherein the jitter buffer has a size selected to maintain jitter below 125 microseconds.
2. A system according to claim 1 , further comprising
a merge circuit for merging the generated FSDU with packet flow data being sent to the packet switch.
3. A system according to claim 1 , further comprising
a decapsulation circuit for processing a generated FSDU passed through the packet switch to provide data to one or more TDM circuits sending data from a port of the packet switch.
4. A system according to claim 1 , wherein
the circuit demultiplexer includes means for accessing a connection table having information representative of the ports associated with a circuit.
5. A system according to claim 1 , further including
a priority switch for associating a routing priority level with a generated FSDU.
6. A system according to claim 1 , wherein
the packet switch includes ports capable of supporting a combination of traffic types.
7. A system according to claim 1 , wherein
traffic types include packet type traffic and TDM type traffic.
8. A system according to claim 1 , further comprising
a dropped-circuit detector for detecting a dropped TDM circuit.
9. A system according to claim 8 , wherein
the FSDU generator responds to the dropped-circuit detector to adjust the contents of the FSDU.
10. A process for passing Time Division Multiplexed (TDM) traffic through a packet switch, comprising
providing a packet switch having a plurality of data ports and being capable of routing Fixed Size Data Unit (FSDU) packets between the plurality of data ports, the packet switch routing the FSDU packets within the packet switch based on header information within respective FSDU packets;
identifying a TDM data flow,
encapsulating the TDM data flow by sorting the TDM data flow into different respective buffer locations,
generating an FSDU that can pass through the packet switch and filling the generated FSDU with data associated with a respective one of the TDM circuits,
generating the header information for routing the generated FSDU to a port associated with the respective one of the TDM circuits,
combining the generated FSDU with a flow of packet data being sent to the packet switch;
allocating bandwidth for generated FSDU traffic to provide a predetermined latency period for routing FSDU traffic through the packet switch;
receiving the FSDU traffic with the predetermined latency period by a jitter buffer, wherein the jitter buffer has a size selected as a function of a minimum and maximum latency of the FSDU traffic; and
reducing variable delays in the FSDU traffic by the jitter buffer;
wherein the time period is set to the TDM frame boundary period.
11. A process according to claim 10 , further comprising
processing a generated FSDU having been passed through the packet switch to reconstruct a TDM data flow circuit at an output port of the packet switch.
12. A process according to claim 11 , further comprising
monitoring the number of TDM circuits within the TDM data flow to identify a change in the number of TDM circuits.
13. A process according to claim 12 , further comprising
altering the contents of the generated FSDU as a function of a detected change in the number of circuits in the TDM data flow.
14. A process according to claim 10 , further comprising
setting a timer to establish a time period for filling the generated FSDU.