IP Library Granted Patent US 7,754,562
Granted Patent B2
US 7,754,562 · App. 12/368,606 · Granted Jul 13, 2010

Semiconductor device comprising capacitor and method of fabricating the same

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Quick Facts
Patent No.
US 7,754,562
App. No.
12/368,606
Filed
Feb 10, 2009
Granted
Jul 13, 2010
Kind
B2
Art Unit
2822
USPC
257/238
Abstract

A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. A semiconductor device organized as just described, permits implementation having a high density of integration while ensuring the capacitor exhibits high reliability and a constant capacitance.

Claims (43)

1. A method of fabricating a semiconductor memory device having a capacitor comprising the steps of:

forming a field effect transistor having a gate electrode, a source region and a drain region, on a major surface of a semiconductor substrate;

forming a first insulating film having a first opening over said field effect transistor;

forming a conductive plug in said first opening, being electrically connected to said source or said drain region of said field effect transistor;

forming a interlayer insulating film above said conductive plug and first insulating film;

forming a second opening in said interlayer insulating film by etching procedure, and

exposing an upper surface of said conductive plug in said opening;

forming a first conductive film along an inner surface of said opening and an upper surface of said interlayer insulating film;

removing said first conductive film over said interlayer insulating film, so as to leave said first conductive film along an inner surface of said opening;

forming a dielectric film on said first conductive film; and

forming a second conductive film on said dielectric film;

wherein said step of forming a interlayer insulating film includes the steps of:

forming a second insulating film, and

forming a third insulating film over said second insulating film, and

said second insulating film has an etching rate larger than the etching rate of said third insulating film.

2. The method of fabricating a semiconductor memory device according to claim 1 , further comprising the step of:

forming a fourth insulating film including a material different from said interlayer insulating film between said first insulating film and said interlayer insulating film,

wherein said step of forming said second opening includes the steps of:

forming a third opening exposing an upper surface of said fourth insulating film and forming a fourth opening exposing an upper surface of said conductive plug through said fourth insulating film.

3. The method of fabricating a semiconductor memory device according to claim 2 ,

wherein said fourth insulating film includes a silicon and a nitrogen.

4. The method of fabricating a semiconductor memory device according to claim 1 ,

wherein an impurity concentration included in said second insulating film is higher than the impurity concentration included in said third insulating film.

5. The method of fabricating a semiconductor memory device according to claim 4 ,

wherein said second insulating film and said third insulating film mainly include silicon and oxygen, and said impurity includes a boron.

6. The method of fabricating a semiconductor memory device according to claim 4 ,

wherein said second insulating film and said third insulating film mainly include silicon and oxygen, and said impurity includes phosphorus.

7. The method of fabricating a semiconductor memory device according to claim 1 ,

wherein said etching procedure includes a wet etching.

8. The method of fabricating a semiconductor memory device according to claim 1 ,

wherein an etchant of said etching procedure includes a hydrofluoric acid.

9. The method of fabricating a semiconductor memory device according to claim 1 ,

wherein said step of forming said first conductive film further includes forming granular crystals on an inner surface of said first conductive film.

10. The method of fabricating a semiconductor memory device according to claim 1 , further comprising the step of:

removing said third insulating film, after said step of removing said first conductive film and before said step of forming said dielectric film.

11. The method of fabricating a semiconductor memory device according to claim 1 ,

wherein said step of removing said first conductive film is executed by CMP or etching without using mask pattern.

12. The method of fabricating a semiconductor memory device according to claim 1 ,

wherein said second insulating film is located at a bottom layer and said third insulating film is located at a top layer in said interlayer insulating film.

13. The method of fabricating a semiconductor memory device according to claim 1 ,

further comprising the step of:

forming a bit line of said semiconductor memory device before said step of forming a first insulating film,

wherein a top surface of said conductive plug is higher than a top surface of said bit line.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 053654 FRAME: 0254. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 10, 2021
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC
Reel/Frame 057454/0045 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED ON REEL 052853 FRAME 0153. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Mar 2, 2021
From: ACACIA RESEARCH GROUP LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 056775/0066 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
Reel/Frame 053654/0254 →
PATENT SECURITY AGREEMENT Recorded Jun 5, 2020
From: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MERTON ACQUISITION HOLDCO LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 052853/0153 →