Download sequencing techniques for circuit configuration data
View Patent ↗Methods, systems, and devices are described for the implementation of a novel architecture to support download sequencing techniques for circuit configuration data. Sets of configuration data from nonvolatile memory may be sequentially transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Different programmable circuit elements may use configuration data, but have different ramp-up times before stable operation. With early download sequence positioning of configuration data, and corresponding immediacy in initiation of operation, certain clock elements are able to commence initiation of operation while remaining clock elements are provided with configuration data from a latter portion of the download sequence.
1. A configuration circuit for configuring circuit elements, the circuit comprising:
a nonvolatile memory array configured to store a set of configuration data for each of a plurality of circuit elements comprising a clock generator circuit;
a control module, communicatively coupled with the nonvolatile memory array and a volatile memory, and configured to control successive transfers, in a predetermined sequence, of each set of configuration data to the volatile memory, wherein in controlling the successive transfers, the control module is configured to:
control transfer of a first set of configuration data corresponding to a power supply; and
control, after transfer of the set of configuration data corresponding to the power supply, transfer of a second set of configuration data corresponding to a phase lock loop; and
the volatile memory, configured to be communicatively coupled with each of the plurality of circuit elements, and configured to receive and store each transferred set of configuration data, wherein one or more of the plurality of circuit elements are adapted to begin operation responsive to receipt of their corresponding set of configuration data and before each set of the configuration data has been transferred.
2. The configuration circuit of claim 1 , wherein the control module, in controlling the successive transfers, is configured to commence the sequence with the first set of configuration data corresponding to a power supply.
3. The configuration circuit of claim 1 , wherein the power supply is operational according to the first set of configuration data while the second set of configuration data is being transferred.
4. The configuration circuit of claim 1 , wherein the control module, in controlling transfer of the second set of configuration data, is configured to:
commence by controlling transfer of analog phase lock loop configuration data; and
initiate, after transfer of the analog phase lock loop configuration data, transfer of digital phase lock loop configuration data.
5. The configuration circuit of claim 1 , wherein the control module, in controlling the successive transfers, is configured to:
initiate, after transfer of the second set of configuration data comprising analog and digital phase lock loop configuration data, transfer of a third set of configuration data corresponding to a system input/output circuit.
6. The configuration circuit of claim 1 , wherein the control module is further configured to control transfer of a set of configuration data for a second of the plurality of circuit elements after initiation of and concurrent with a stable operational state in a first of the plurality of circuit elements, the first circuit element initiating operation upon receipt of corresponding configuration data.
7. The configuration circuit of claim 1 , wherein the control module is configured to modify the predetermined order.
8. The configuration circuit of claim 1 , wherein the control module comprises:
an interface controller configured to acquire configuration data from the nonvolatile memory array; and
a storage controller configured to transfer, in the sequence, the configuration data from the nonvolatile memory array to the volatile memory.
9. The configuration circuit of claim 8 , wherein,
the interface controller is further configured to produce control signaling to the storage controller;
the storage controller is further configured to produce control signaling to the volatile memory;
the volatile memory comprises a volatile register bank;
the transfers are performed using a serial interface; and
the interface controller and the storage controller are on the same monolithic semiconductor substrate.
10. A programmable clock generator comprising:
a nonvolatile memory array configured to store a set of configuration data for each of a plurality of circuit elements;
a control module, communicatively coupled with the nonvolatile memory array and a volatile memory, and configured to control successive transfers, in a predetermined sequence, of each set of configuration data to the volatile memory, wherein in controlling the successive transfers, the control module is configured to:
commence the sequence with a first set of configuration data corresponding to a specified voltage level for a power supply of the clock generator; and
initiate, after completion of the transfer of the set of configuration data corresponding to the specified voltage level for the power supply of the clock generator, transfer of a second set of configuration data corresponding to specifications for a crystal oscillator;
the volatile memory configured to store each transferred set of configuration data when received; and
the plurality of circuit elements, communicatively coupled with the volatile memory, and configured to generate a clock signal according to the transferred sets of configuration data.
11. The programmable clock generator of claim 10 , wherein the crystal oscillator is operational according to the second set of configuration data while a third set of configuration data is being transferred corresponding to divide by logic for a phase lock loop.
12. The programmable clock generator of claim 10 , wherein the control module, in controlling transfer of the sets of configuration data, is configured to
control transfer of analog phase lock loop configuration data; and
initiate, upon transfer of the analog phase lock loop configuration data, transfer of digital phase lock loop configuration data comprising divide by logic information.
13. The programmable clock generator of claim 10 , wherein,
the predetermined order is programmable;
the volatile memory comprises a volatile register bank; and
the clock generator is used for a printer, copier, liquid crystal display, portable computer, mobile phone, router, switch, storage device, high definition television, or other stand alone or embedded computing device.
14. A method of configuring a plurality of circuit elements comprising a clock generator circuit, the method comprising:
storing a set of configuration data for each of a plurality of circuit elements in nonvolatile memory;
transferring, in a predetermined sequence, each set of configuration data from the nonvolatile memory to a volatile memory, wherein the transferring step comprises:
commencing the predetermined sequence with transfer of the set of configuration data corresponding a first circuit element, the first circuit element comprising a power supply;
initiating operation of the power supply responsive to completion of the transfer of configuration data corresponding to the power supply; and
initiating, after completion of the transfer of configuration data corresponding the power supply, transfer of the set of configuration data corresponding the second circuit element, the second circuit element comprising a phase lock loop;
storing each transferred set of configuration data in the volatile memory; and
operating the power supply while the set of configuration data for the phase lock loop is being transferred.
15. The method of claim 14 , wherein the transfer of the set of configuration data corresponding to the element phase lock loop comprises:
transferring analog phase lock loop configuration data; and
initiating, after completion of the transfer of the analog phase lock loop configuration data, transfer of digital phase lock loop configuration data.
16. The method of claim 14 , wherein the transferring step comprises:
initiating, upon completing transfer of a set of configuration data comprising analog and digital phase lock loop configuration data, transfer of a set of configuration data corresponding to a system input/output circuit, wherein the analog and digital phase lock loop comprises the first circuit element and the system input/output circuit comprises the second circuit element.
17. The method of claim 14 , wherein the transferring step comprises:
completing transfer of the set of configuration data for the second circuit element before the first circuit element has reached a stable operating state.