A programmable volatile memory cell has a reset device in communication with a bit store. The reset device may produce a high or low logic state within a latch loop when activated by an assertive logic level on a reset line. A set of mask programmable vias may be provided on a single mask layer in a semiconductor fabrication process for the memory cell. A program-selectable one of two sets of vias may communicate with one reset device to the reset line and the other reset device to ground. In this way a single and programmatically determinable logic state may be produced in the memory cell with reset signaling. Otherwise, the memory cell is capable of retaining a logic state according to read/write processes. The memory cell may be implemented in an array where all or some of the cells may be reset at once.
1. An array of memory cells comprising:
a first memory cell comprising:
a bit store, configured to store a logic value;
a first reset device, communicatively coupled with the bit store, configured to set the bit store to a predefined logic value when triggered, wherein the predefined logic value is independently configurable with respect to at least one other memory cell of the array; and
a selector element configurable to determine the predefined logic value.
2. The array of memory cells of claim 1 , further comprising:
a via element, wherein the selector element is configurable in a first state and a second state, wherein in the first state the selector element is coupled to the via element, and wherein in the second state the selector element is not coupled to the via element.
3. The array of memory cells of claim 2 , further comprising a reset transmission device configured to transmit a reset signal to the via element, wherein when the selector element is configured in the first state, the selector element sets the bit store to the predefined logic value in response to the reset signal.
4. The array of memory cells of claim 1 , wherein the selector element is a via, a trace, or a combination thereof.
5. The array of memory cells of claim 1 , wherein the selector element is configured to be coupled with either a first portion of the bit store setting the predefined logic value to a first logic value or to a second portion of the bit store setting the predefined logic value to a second logic value.
6. The array of memory cells of claim 1 , wherein the first memory cell is a volatile form of storage.
7. The array of memory cells of claim 1 , wherein the first memory cell comprises a latch loop.
8. The array of memory cells of claim 1 , integrated within a field-programmable read-only memory (ROM) device.
9. The array of memory cells of claim 1 , wherein the selector element is configurable to set the predefined logic value to a first logic value, and wherein the first memory cell further comprises a second selector element configurable to set the predefined logic value to a second logic value.
10. The array of memory cells of claim 1 , further comprising:
a second memory cell including:
a second bit store, configured to store a logic value; and
a second reset device, communicatively coupled to the second bit store and configured to set the second bit store to a predefined logic value when triggered, wherein the predefined logic value of the second memory cell is independently configurable with respect to the predefined logic value of the first memory cell.
11. An array of memory cells, each of at least a subset of the array of memory cells comprising:
a bit store, configured to store a logic value;
a first reset device, communicatively coupled with the bit store, and configured to set the bit store to a predefined logic value when triggered, wherein the predefined logic value for the each of at least the subset of the array of memory cells is independently configurable with respect to at least one other memory cell of the array;
a reset transmission device, communicatively coupled with the first reset device, configured to trigger the first reset device with a reset signal; and
a second reset device, the second reset device communicatively coupled with the reset transmission device in the alternative to the first device, the predefined logic value dictating whether the first reset device or the second reset device is communicatively coupled with the reset transmission device.
12. The array of memory cells of claim 11 , for the each of at least the subset of the memory cells further comprising a second selector element configured to communicatively couple with the second reset device, the second selector element communicatively coupling the second reset device to a static signal or the second selector element communicatively coupling the second reset device to the reset transmission device.
13. The array of memory cells of claim 12 , the second reset device further configured to be communicatively coupled with electrical ground, such that the second reset device has a permanent state.