Level shifter circuit
View Patent ↗A level shifter circuit which amplifies the amplitude of an input signal, includes a CMOS inverter which is composed of a p-type transistor and an n-type transistor, a first and a second capacitor one electrode of each of which is connected to the gate of the p-type transistor and that of the n-type transistor, respectively, a first switch which supplies the input signal to the other electrodes of the first and second capacitors, a second switch which applies a direct-current voltage whose amplitude is nearly half of the amplitude of the input signal to the other electrodes of the first and second capacitors, and a third and a fourth switch which apply a first and a second preset voltage to one electrode of each of the first and second capacitors, respectively.
1. A level shifter circuit which amplifies the amplitude of an input signal, the level shifter circuit comprising:
a CMOS inverter which is composed of a p-type transistor and an n-type transistor;
a first and a second capacitor one electrode of each of which is connected to the gate of the p-type transistor and that of the n-type transistor, respectively;
a first switch which supplies the input signal to the other electrodes of the first and second capacitors;
a second switch which applies a direct-current voltage whose amplitude is nearly half of the amplitude of the input signal to the other electrodes of the first and second capacitors; and
a third and a fourth switch which apply a first and a second preset voltage to one electrode of each of the first and second capacitors, respectively.
2. The level shifter circuit according to claim 1 , wherein the first and second preset voltages are configured to set independently.
3. The level shifter circuit according to claim 2 , wherein the level shifter circuit is configured to operate in the following two modes:
an operating point reset mode in which the level shifter circuit applies not only the first and second preset voltages to one electrode of each of the first and second capacitors, respectively, but also the direct-current voltage to the other electrodes of the first and second capacitors, and
a level shifter operation mode in which the level shifter circuit amplifies the amplitude of the input signal and outputs the amplified signal at the COMS inverter.
4. The level shifter circuit according to claim 3 , wherein control is performed in such a manner that
the second switch, third switch, and fourth switch go on in the operating point reset mode, and
the first switch goes on in the level shifter operation mode.