Programmable IO architecture

1. A buffer device coupled to at least one input/output port of an integrated circuit, the buffer device comprising:

a plurality of control inputs capable of receiving configuration programming; and

at least one input/output circuit capable of being configured in a directional sense of communication by the configuration programming received at the plurality of control inputs, the at least one input/output circuit capable of being:

configured as at least one input circuit capable of being further configured to provide input logic switching level thresholds according to the configuration programming, and

configured as at least one output circuit capable of being further configured to provide a slew rate that is configurable independently of an output drive strength and an output drive strength that is configurable independently of the slew rate according to the configuration programming.

2. The buffer device of claim 1 , wherein the configuration programming is a sequence of signaling containing electrical levels capable of being determined by the buffer device and producing particular circuit element selection effecting a particular operational configuration.

3. The buffer device of claim 1 , wherein the at least one input/output circuit is configured by the configuration programming to be an input buffer.

4. The buffer device of claim 3 , wherein the configuration programming configures the at least one input/output circuit to logically switch, in response to input signaling, at certain logic switching thresholds.

5. The buffer device of claim 3 , wherein the configuration programming configures the at least one input/output circuit to selectively connect an input signal to one or more signal destinations.

6. The buffer device of claim 5 , wherein the one or more signal destinations being common buses in electrical communication with a plurality of buffers.

7. The buffer device of claim 1 , wherein the at least one input/output circuit is configured by the configuration programming to be an output buffer.

8. The buffer device of claim 7 , wherein the configuration programming configures the at least one output circuit to have certain output drive strengths.

9. The buffer device of claim 7 , wherein the configuration programming configures the at least one input/output circuit to have an inversion in polarity of signaling being transmitted.

10. The buffer device of claim 7 , wherein the configuration programming configures a pull-up drive strength or a pull-down drive strength of the at least one output circuit independently.

11. The buffer device of claim 7 , wherein the configuration programming configures the at least one output circuit to have additional delay introduced to the output signal path, the magnitude of delay introduced being further configured by the configuration programming.

12. The buffer device of claim 7 , wherein the output circuit includes at least one slew rate control component that controls an output slew rate of the at least one output circuit, responsive to the configuration programming, by controlling a signal that drives at least one output transistor so as to enable the slew rate to be changed without substantially affecting the output drive strength.

13. An integrated circuit buffer comprising:

a plurality of control inputs used to receive configuration programming, the configuration programming capable of electrically configuring the buffer as either one or two inputs or a differential output buffer, said input buffers having a plurality of input switching thresholds, and

an inversion block coupled to a single ended output, the inversion block, responsive to the configuration programming, configures the buffer as a differential output buffer by inverting a signal output from the single-ended-output so as to create a complimentary-signal relative to another true-signal that is output from another single-ended-output so as to create a differential output between the two single-ended-outputs, said output buffer having a plurality of output drive strengths each controlled by one or more of said control inputs,

wherein a slew rate of a rising output signal or a falling output signal from the integrated circuit buffer, configured as a differential output buffer, is further configured, independently of drive strength, by the configuration programming.

14. The integrated circuit buffer of claim 13 , wherein the integrated circuit buffer configured as either one or two input buffers is capable of having the buffered input signal selectively coupled to one or more input destinations, the one or more input destinations configured by the configuration programming.

15. The integrated circuit buffer of claim 14 , wherein the one or more input destinations are common buses in electrical communication with a plurality of buffers.

16. The integrated circuit buffer of claim 13 , wherein the configuration programming independently configures a pull-up drive strength and a pull-down drive strength of the at least one output circuit independently.

17. The integrated circuit buffer of claim 13 , wherein additional delay being independently added to the true-signal output path or the complimentary-signal output path of the integrated circuit buffer configured as a differential output buffer, a magnitude of delay being configured according to the configuration programming.

18. The integrated circuit buffer of claim 13 , wherein the slew rate of the rising output signal or the falling output signal is configured substantially independent of the output impedance.

19. The integrated circuit buffer of claim 13 , wherein a signal source is coupled from common buses in electrical communication with at least one of a plurality of buffers to one of a plurality of integrated circuit buffers configured as a differential output buffer.

20. A method of configuring a buffer device coupled to at least one input/output port of an integrated circuit, the method comprising:

receiving a plurality of configuration programming from at least one control input associated with at least one further input/output port of the integrated circuit;

determining a selection of circuit elements within the buffer device being the focus of the configuration programming;

selecting at least one output circuit element being the focus of the configuration programming; and

activating the at least one output circuit element being the focus of the configuration programming, the activating including modifying characteristics of the output circuit element capable of being further configured to provide a slew rate that is configurable independently of an output drive strength and an output drive strength that is configurable independently of the slew rate according to the configuration programming.

21. A method of configuring a buffer device coupled to at least one input/output port of an integrated circuit, the method comprising:

receiving configuration programming from at least one control input associated with at least one further input/output port of the integrated circuit that sets the buffer device as an input buffer device;

receiving configuration programming that defines whether the buffer device is a three-level or a two-level input buffer device;

determining a selection of circuit elements within the buffer device being the focus of the configuration programming;

selecting at least one circuit element being the focus of the configuration programming that sets the buffer device as an input buffer device;

activating the at least one circuit element being the focus of the configuration programming to be an input buffer with an inbound communication direction sense; and

enabling another circuit element, responsive to the configuration programming defining the buffer device as a two-level or a three-level input buffer device.

22. The method of configuring a buffer device of claim 21 , wherein enabling another circuit element includes enabling a second comparator in addition to an already enabled first comparator so as to enable an input signal to the buffer device to be compared, simultaneously, with two reference voltages so as to generate a two-bit output that is decodable into three logic states that identify three voltage levels of the input signal.

23. The method of configuring a buffer device of claim 22 further comprising:

receiving configuration programming that defines a particular intermediate voltage level; and

altering a voltage of the input signal that is applied to the two comparators responsive to the programming so as to effectuate the particular intermediate voltage level.

24. A method of configuring a buffer device coupled to at least one input/output port of an integrated circuit, the method comprising:

receiving a plurality of configuration programming from at least one control input associated with at least one further input/output port of the integrated circuit that sets the buffer device as an output buffer device;

receiving configuration programming that defines a slew rate;

determining a selection of circuit elements within the buffer device being the focus of the configuration programming that sets the buffer device as an output buffer device;

selecting at least one circuit element being the focus of the configuration programming that sets the buffer device as an output buffer device;

activating the at least one circuit element being the focus of the configuration programming to be an output buffer with an outbound communication direction sense; and

controlling, responsive to the configuration programming that defines a slew rate, a drive signal that drives an output transistor of the buffer device so as to alter a switching rate of the output transistor independently of a drive strength of the output transistor.

25. The method of configuring a buffer device of claim 24 further comprising:

activating at least one output buffer to have certain output drive strengths.

26. The method of configuring a buffer device of claim 24 further comprising:

activating at least one output buffer to have an inversion of the polarity of the signaling being transmitted.

27. The method of configuring a buffer device of claim 24 further comprising:

activating at least one output buffer to have additional delay introduced to the output signal path.