Systems and methods for memory retention across resets

1. A computer system, comprising:

a processor;

a dynamic random access memory (DRAM) module coupled to the processor, wherein a predetermined portion of the DRAM module is designated as retentive DRAM (RDRAM); and

a refresh module coupled to the DRAM module and operable to periodically refresh the memory cells of the DRAM module;

wherein the refresh module is configured to provide periodic refreshes to the memory cells of the DRAM module during a reboot of the computer system such that contents of the RDRAM are preserved during the reboot, the reboot including at least one boot sequence executed by the computer system.

2. The computer system of claim 1 , wherein the processor is configured to execute instructions that function to write data to the contents of the RDRAM.

3. The computer system of claim 1 , wherein the refresh module is configured to provide refreshes to the memory cells of the DRAM module during a reboot that is initiated by the occurrence of a fault condition.

4. The computer system of claim 3 , further comprising:

a software module, executable by the computer system, that is operable to initiate a transition into a standby state in response to the fault condition detected by software, and wherein the software module is further operable to cause a reboot of the computer system.

5. The computer system of claim 4 , further comprising a mechanism that is operable to detect the fault condition, wherein the mechanism is further operable to determine that the reboot did not occur, and in response to the determination, to initiate a hard reset of the computer system.

6. The computer system of claim 3 , further comprising:

a software module, executable by the computer system, that is operable to assert a non-maskable interrupt (NMI) in response to a fault condition; and

an NMI handler module, executable by the computer system, that is operable to cause a reboot of the computer system;

wherein the contents of the RDRAM are preserved during the reboot.

7. The computer system of claim 6 , further comprising a mechanism that is operable to detect the fault condition, wherein the mechanism is further operable to determine that the reboot did not occur, and in response to the determination, to initiate a hard reset of the computer system.

8. A method, comprising:

storing data in a predefined portion of a dynamic random access memory (DRAM) module of a computer system; and

periodically refreshing the memory cells of the DRAM module during a reboot of the computer system such that the contents of the predefined portion are preserved during the reboot, the reboot including at least one boot sequence executed by the computer system.

9. The method of claim 8 , wherein the data includes information relating to events of the computer system.

10. The method of claim 9 , further comprising, after the reboot, reading the data from the predefined portion of the DRAM module.

11. The method of claim 10 , wherein the reading is performed by an application running on the computer system.

12. The method of claim 8 , further comprising:

initiating a transition into a standby state to place the memory into self refresh, wherein the initiating results from at least one of a fault condition or an exception condition that is detected by software.

13. The method of claim 8 , further comprising:

asserting a non-maskable interrupt (NMI) in response to a fault condition that is detected external to a processor of the computer; and

executing instructions to reboot the computer system while preserving data stored on the DRAM module.

14. The method of claim 13 , wherein the asserting step is initiated by one of the expiration of a watchdog timer (WDT) and a command received from a component external to the computer system.

15. A method for preserving data stored in a dynamic random access memory (DRAM) module of computer system during a reboot, the method comprising:

detecting a fault condition in the computer system when the computer system is running in a normal operating state;

first transitioning the computer system into a standby state in response to the detecting of the fault condition;

second transitioning the computer system automatically from the standby state to a soft off state; and

third transitioning the computer system from the soft off state to the normal operating state the third transitioning including execution of at least one boot sequence;

wherein the computer system is configured to preserve the data located in a predetermined portion of the DRAM module through the first, second, and third transitioning steps.

16. The method of claim 15 , further comprising writing data to the predetermined portion of the DRAM module.

17. The method of claim 16 , wherein the computer system is configured such that the writing of data is non-cacheable.

18. The method of claim 15 , further comprising a mechanism to automatically initiate the third transitioning step.

19. The method of claim 15 , further comprising asserting a non-maskable interrupt (NMI) in response to the detecting the fault condition step, wherein the first transitioning step is initiated by an NMI handler.

20. The method of claim 15 , wherein the computer system conforms to the Advanced Configuration and Power Interface (ACPI) specification, and wherein the normal operating state is the ACPI S0 state, the standby state is the ACPI S3 state, and the soft off state is the ACPI S5 state.