IP Library Granted Patent US 7,795,083
Granted Patent B2
US 7,795,083 · App. 12/371,879 · Granted Sep 14, 2010

Semiconductor structure and fabrication method thereof

Assignee: Vanguard International Semiconductor Corporation
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Quick Facts
Patent No.
US 7,795,083
App. No.
12/371,879
Granted
Sep 14, 2010
Kind
B2
Abstract

The invention provides a method for forming a semiconductor structure. A plurality of first type well regions is formed in the first type substrate. A plurality of second type well regions and a plurality of second type bar doped regions are formed in the first type substrate by a doping process using a mask. The second type bar doped regions are diffused to form a second type continuous region by annealing. The second type continuous region is adjoined with the first type well regions. A second type dopant concentration of the second type continuous region is smaller than a second type dopant concentration of the second type bar doped regions. A second type source/drain region is formed in the second type well region.

Claims (26)

1. A method for forming a semiconductor structure, comprising:

providing a first conductivity type substrate;

forming a plurality of first conductivity type well regions in the first conductivity type substrate by doping a first conductivity type dopant in the first conductivity type substrate;

forming a plurality of second conductivity type well regions and a plurality of second conductivity type bar doped regions in the first conductivity type substrate by a doping process using a mask;

diffusing the second conductivity type bar doped regions to form a second conductivity type continuous region by annealing, wherein the second conductivity type continuous region adjoins the first conductivity type well regions, and a second conductivity type dopant concentration of the second conductivity type continuous region is smaller than a second conductivity type dopant concentration of the second conductivity type bar doped regions; and

forming a second conductivity type source/drain region in the second conductivity type well region.

2. The method for forming the semiconductor structure as claimed in claim 1 , wherein thicknesses W of the second conductivity type bar doped regions are bigger than 0.5 m.

3. The method for forming the semiconductor structure as claimed in claim 2 , wherein a separated distance S between the adjacent second conductivity type bar doped regions is smaller than 10 μm.

4. The method for forming the semiconductor structure as claimed in claim 3 , wherein the thickness W and the separated distance S are equal.

5. The method for forming the semiconductor structure as claimed in claim 3 , wherein the thickness W and the separated distance S are different.

6. The method for forming the semiconductor structure as claimed in claim 1 , further comprising forming a first conductivity type heavily doped region in the first conductivity type well region.

7. The method for forming the semiconductor structure as claimed in claim 1 , further comprising forming an isolation structure on the second conductivity type well region.

8. The method for forming the semiconductor structure as claimed in claim 7 , wherein the isolation structure is deposited on the first conductivity type well region.

9. The method for forming the semiconductor structure as claimed in claim 1 , wherein the second conductivity type bar doped region is deposited between the first conductivity type well regions.

10. The method for forming the semiconductor structure as claimed in claim 9 , wherein the first conductivity type well regions are deposited between the second conductivity type well regions.

11. The method for forming the semiconductor structure as claimed in claim 1 , wherein each of the second conductivity type well regions and each of the second conductivity type bar doped regions are separated by the first conductivity type substrate.

12. A semiconductor structure, comprising:

a first conductivity type substrate;

a plurality of first conductivity type well regions formed in the first conductivity type substrate by doping a first conductivity type dopant in the first conductivity type substrate;

a plurality of second conductivity type well regions formed in the first conductivity type substrate;

a second conductivity type continuous doped region adjoined with the first conductivity type well regions, wherein a second conductivity type dopant concentration of the second conductivity type continuous doped region is smaller than a second conductivity type dopant concentration of the second conductivity type well region; and

a second conductivity type source/drain formed in the second conductivity type well region.

13. The semiconductor structure as claimed in claim 12 , further comprising a first conductivity type heavily doped region formed in the first conductivity type well region.

14. The semiconductor structure as claimed in claim 12 , further comprising an isolation structure formed on the second conductivity type well region.

15. The semiconductor structure as claimed in claim 14 , wherein the isolation structure is deposited on the first conductivity type well region.

16. The semiconductor structure as claimed in claim 12 , wherein the first conductivity type well regions are deposited between the second conductivity type well regions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2009
From: TSAI, HUNG-SHERN; TU, SHANG-HUI; LIN, SHIN-CHENG
To: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
Reel/Frame 022283/0748 →
Continuity (1)
Related Publication 20100207174A1 · Aug 19, 2010