Random access decoder

1. A readout circuit comprising at least one decoder, each decoder comprising a plurality of decoder circuit elements and means for applying an input signal to each of the decoder circuit elements, wherein each decoder circuit element has a unique electronic address and a binary data output and places data on its binary data output only when the unique electronic address of a particular decoder circuit element matches the applied input signal, the unique electronic address of each of the plurality of decoder circuit elements being electronically loadable into each of the decoder circuit elements, wherein the readout circuit is adapted for use with an imaging array and further wherein at least two of the decoder circuits element are physically identical.

2. A readout circuit as claimed in claim 1 , wherein each decoder circuit element comprises equivalent electrical components electrically connected in the same arrangement.

3. A readout circuit as claimed in claim wherein all the decoder circuit elements are formed from physically identical circuit designs.

4. A readout circuit as claimed in claim 1 wherein each decoder circuit element comprises an adder component, and where the adder components of each decoder circuit element are connected in series such that each decoder circuit element is electronically loaded with a unique electrical address.

5. A readout circuit as claimed in claim 1 wherein each decoder circuit element comprises a comparator component, and where the comparator component of each decoder circuit element determines whether the unique electrical address of a particular decoder circuit matches the applied input signal.

6. A readout circuit as claimed in claim 1 and arranged to read data from an imaging array having a number of rows and/or columns.

7. A readout circuit according to claim 1 arranged to read data from an imaging array comprising a linear array of pixel elements.

8. A readout circuit according to claim 1 arranged to read data from an imaging array comprising a two dimensional array of pixel elements operably connected along row and column lines.

9. A readout circuit as claimed in claim 1 wherein the readout circuit is fabricated on a single silicon chip.

10. A readout circuit as claimed in claim 1 fabricated using CMOS techniques.

11. An infra-red detector having a readout circuit as claimed in claim 1 .

12. A readout circuit comprising at least one decoder, each decoder comprising a plurality of decoder circuit elements and means for applying an input signal to each of the decoder circuit elements, wherein each decoder circuit element has a unique electronic address and a binary data output and places data on its binary data output only when the unique electronic address of a particular decoder circuit element matches the applied input signal, the unique electronic address of each of the plurality of decoder circuit elements being electronically loadable into each of the decoder circuit elements, wherein the readout circuit is adapted for use with an imaging array and further wherein at least two of the decoder circuits element are electrically identical.

13. A readout circuit as claimed in claim 12 wherein each decoder circuit element comprises an adder component, and where the adder components of each decoder circuit element are connected in series such that each decoder circuit element is electronically loaded with a unique electrical address.

14. A readout circuit formed on an integrated circuit comprising at least one decoder, each decoder comprising a plurality of decoder circuit elements and means for applying an input signal to each of the decoder circuit elements, wherein each decoder circuit element has a unique electronic address and a binary data output and places data on its binary data output only when the unique electronic address of a particular decoder circuit element matches the applied input signal, the unique electronic address of each of the plurality of decoder circuit elements being electronically loadable into each of the decoder circuit elements, wherein at least two of the decoder circuits element are physically identical.

15. A readout circuit as claimed in claim 14 wherein the integrated circuit is a complimentary metal oxide semiconductor (CMOS) integrated circuit.

16. A readout circuit comprising at least one decoder, each decoder comprising a plurality of decoder circuit elements and means for applying an input signal to each of the decoder circuit elements, wherein each decoder circuit element has a unique electronic address and a binary data output and, places data on its binary data output only when the unique electronic address of a particular decoder circuit element matches the applied input signal, the unique electronic address of each of the plurality of decoder circuit elements being electronically loadable into each of the decoder circuit elements, wherein the readout circuit is adapted for use with an imaging array and further comprises a shift register associated with each decoder, each decoder being arranged to load the shift register associated therewith at any point along its length.

17. A readout circuit as claimed in claim 16 wherein each decoder circuit element comprises an adder component, and where the adder components of each decoder circuit element are connected in series such that each decoder circuit element is electronically loaded with a unique electrical address.