IP Library Granted Patent US 8,097,951
Granted Patent B2
US 8,097,951 · App. 12/379,793 · Granted Jan 17, 2012

Integrated circuit having wiring layer and a pattern in which a gap is formed and method for manufacturing same

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Quick Facts
Patent No.
US 8,097,951
App. No.
12/379,793
Granted
Jan 17, 2012
Kind
B2
Abstract

When an integrated circuit having an interlayer insulation film built up on top of a wiring layer is subjected to a heat treatment, it is unlikely that a void formed in the interlayer insulation film will rupture in a portion wherein are connected a narrow gap between wirings and a wide open part contiguous therewith. A corner part of a wiring positioned at a portion where a gap and an open part are connected is chamfered, and an end part of the gap is shaped so as to widen toward the open part. Providing the widening end part in the gap thus mitigates any discontinuity in the built up interlayer insulation film between the gap and the open part. As a result, the interlayer insulation film does not readily seal off an end of a void formed in the gap.

Claims (33)

1. An integrated circuit comprising:

a wiring layer laminated on a substrate and having a pattern in which is formed a gap for forming a narrow trench and a wide open part contiguous with the gap; and

an interlayer insulation film built up so as to cover the wiring layer; wherein

the pattern of the wiring layer has a corner part present in a portion in which the gap and the open part are connected, the corner part is chamfered, and an end part of the gap is formed in a shape that widens toward the open part;

the chamfered corner part has a first edge parallel to the narrow trench, a second edge that is facing the wide open part and is perpendicular to the first edge, and a slanted edge diagonally crossing each of the first edge and the second edge; and

a width of a part of the gap adjacent to the slanted edge at a position along the gap monotonically increases as the position moves closer to a boundary of the open part defined by an extended line of the second edge.

2. The integrated circuit of claim 1 , wherein

the interlayer insulation film is laminated to a thickness at which all of the gap except the end part is buried beneath the interlayer insulation film.

3. The integrated circuit of claim 2 , wherein

the end part of the gap expands toward the open part up to a width at which the built-up interlayer insulation film forms an indentation inside the gap.

4. The integrated circuit of claim 1 , wherein

a void is formed in the interlayer insulation film at a location that does not include the end part but otherwise corresponds to the gap.

5. The integrated circuit of claim 4 , wherein

a recess is formed in the interlayer insulation film in a wide portion of the end part of the gap;

the void extends toward the end part of the gap, and at an unspecified point on the end part the void opens on a top part thereof and changes into the recess.

6. A method for manufacturing an integrated circuit having a wiring layer laminated on a substrate and having a pattern in which is formed a gap for forming a narrow trench and a wide open part contiguous with the gap, and an interlayer insulation film built up so as to cover the wiring layer, the method comprising:

a wiring layer patterning step for patterning the wiring layer laminated on the substrate, and forming the pattern in which a corner part is present in a portion in which the gap and the open part are connected, the corner part is chamfered, and an end part of the gap is formed in a shape that widens toward the open part, wherein the chamfered corner part has a first edge parallel to the narrow trench, a second edge that is facing the wide open part and is perpendicular to the first edge, and a slanted edge diagonally crossing each of the first edge and the second edge; and

monotonically increasing a width part of the gap adjacent to the slanted edge at a position along the gap as the position moves closer to a boundary of the open part defined by an extended line of the second edge.

7. The method for manufacturing an integrated circuit of claim 6 , comprising an interlayer insulation film laminating step for laminating on the patterned wiring layer the interlayer insulation film of a film thickness at which all of the gap except the end part is buried beneath the interlayer insulation film.

8. The method for manufacturing an integrated circuit of claim 7 , wherein

the end part of the gap expands toward the open part up to a width at which the built-up interlayer insulation film forms an indentation inside the gap.

9. An integrated circuit comprising:

a wiring layer laminated on a substrate and having a pattern in which is formed a gap for forming a narrow trench and a wide open part contiguous with the gap; and

an interlayer insulation film built up so as to cover the wiring layer, wherein

the pattern of the wiring layer has a corner part present in a portion in which the gap and the open part are connected, the corner part is chamfered to form an end part of the gap into a shape that widens toward the open part;

the interlayer insulation film is laminated to a thickness at which all of the gap except the end part is buried beneath the interlayer insulation film;

the interlayer insulation film that has the laminated thickness forms a recess inside the open part;

the end part of the gap expands toward the open part up to a width at which the built-up interlayer insulation film that has the laminated thickness forms an indentation inside the gap, the indentation leads into the recess formed inside the open part;

the chamfered corner part has a first edge parallel to the narrow trench, a second edge that is facing the wide open part and is perpendicular to the first edge, and a slanted edge diagonally crossing each of the first edge and the second edge; and

a width of a part of the gap adjacent to the slanted edge at a position along the gap monotonically increases as the position moves closer to a boundary of the open part defined by an extended line of the second edge.

10. The integrated circuit of claim 9 , wherein

a thickness of the interlayer insulation film is more than one-half of a width of the gap except the end part; and

the end part of the gap expands up to a width of more than twice of the thickness of the interlayer insulation film.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 054090, FRAME 0617 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064081/0167 →
SECURITY INTEREST Recorded Oct 16, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 054090/0617 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033813 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 21, 2015
From: SYSTEM SOLUTIONS CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034816/0510 →
CHANGE OF NAME Recorded Dec 3, 2014
From: SANYO SEMICONDUCTOR CO., LTD
To: SYSTEM SOLUTIONS CO., LTD.
Reel/Frame 034537/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2014
From: SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033813/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2009
From: MATSUDA, KATSUSHI
To: SANYO ELECTRIC CO., LTD.; SANYO SEMICONDUCTOR CO., LTD.
Reel/Frame 022363/0407 →