Substrate bias feedback scheme to reduce chip leakage power
View Patent ↗Disclosed is an improved substrate bias feedback circuit, and a method for operating the same.
1. A substrate bias circuit, comprising:
at least one baseline transistor having a plurality of terminals and a body;
a current source that provides a current output to at least one terminal of the base line transistor; and
a charge pump circuit that applies a reverse body bias to the body of the base line transistor, the reverse body bias varying in response to a difference between a reference current and a current through the baseline transistor, wherein the charge pump circuit includes at least one charge pump cell that generates the reverse body bias in response to a control clock signal, and an analog clock driver that varies the control clock signal in response to the difference between the reference current and the current through the baseline transistor.
2. The substrate bias circuit of claim 1 , wherein:
the baseline transistor has a gate and a source-drain path coupled between the current source and a first power supply node.
3. The substrate bias circuit of claim 1 , wherein:
the current source includes a source transistor of a conductivity type different from that of the at least one baseline transistor, the source transistor having a gate coupled to receive a reference bias voltage, and a source-drain path coupled to the baseline transistor.
4. The substrate bias circuit of claim 3 , wherein:
the current source further includes a bias transistor of the same conductivity type as the source transistor, the bias transistor having a gate coupled to receive the reference bias voltage, and a reference bias amplifier having an output that provides the reference bias voltage, a first input coupled to receive an input reference voltage, and a second input coupled to the bias transistor by a feedback path.
5. The substrate bias circuit of claim 1 , further including:
a control amplifier having an output that provides an analog control voltage to the analog clock driver, a first input coupled to the baseline transistor, and a second input coupled to a reference voltage.
6. The substrate bias circuit of claim 5 , wherein:
the analog clock driver varies the amplitude of the control clock signal in response to the analog control voltage.
7. A substrate bias circuit, comprising:
a charge pump that drives a substrate node to a reverse body bias voltage in response to at least one clock control signal;
an analog clock driver that generates at least one output clock signal in response to a periodic input clock signal, and varies the amplitude of the output clock signal in response to a node voltage; and
a bias amplifier that generates the node voltage in response to a leakage current through at least one base line transistor, the baseline transistor having a body that receives the reverse body bias voltage.
8. The substrate bias circuit of claim 7 , wherein:
the analog clock driver includes at least one bias device coupled between a clock logic circuit and a power supply, the bias device having an impedance controlled by the node voltage.
9. The substrate bias circuit of claim 7 , wherein:
the bias amplifier has an output that provides the node voltage, a first input coupled to the baseline transistor, and a second input coupled to a reference voltage.
10. The substrate bias circuit of claim 7 , further including:
the analog clock driver circuit disables the output clock signal in response to an enable signal; and
a clamp circuit that generates the enable signal in response to the reverse body bias voltage exceeding a predetermined limit.
11. The substrate bias circuit of claim 10 , wherein:
the clamp circuit includes a comparator having an output that provides the enable signal, a first input coupled to a reference voltage, and a second input coupled to the reverse body bias voltage.
12. The substrate bias circuit of claim 11 , wherein:
the reverse body bias voltage is coupled to the second input of the comparator by a variable impedance.
13. The substrate bias circuit of claim 7 , further including:
a current source transistor that receives a reference bias voltage at its gate;
the baseline transistor has a source-drain path connected in series with the source-drain path of the current source transistor; and
the bias amplifier has an input coupled to a node between the source-drain paths of the current source transistor and the baseline transistor.
14. A method, comprising:
generating an analog control bias voltage in response to a comparison between a reference current and a leakage current flowing through at least one baseline transistor, the baseline transistor having a body the receives a reverse body bias voltage; and
varying the reverse body bias voltage in response to the analog control bias voltage, wherein generating the analog control bias voltage includes generating a compare input voltage in response to a difference between the reference current and the leakage current through the baseline transistor, comparing the compare input voltage to a reference voltage to generate a compare result, and increasing or decreasing the reverse body bias voltage in response to the compare result.
15. The method of claim 14 , further including:
generating the analog control bias voltage includes varying a compare node potential based on a difference between current capacity of a current source and the baseline transistor.
16. The method of claim 15 , wherein:
generating the analog control bias voltage further includes the current capacity of the current source being established by a reference bias voltage, and the current capacity of the baseline transistor varying in response to the reverse body bias voltage.
17. The method of claim 14 , wherein:
varying the reverse body bias voltage includes in response to the comparison between the reference current and the leakage current, modulating a power supply to at least a portion of a charge pump circuit that generates the reverse body bias voltage.
18. The method of claim 14 , further including:
stopping the reverse body bias voltage when the reverse body bias voltage exceeds at least one limit.