High entropy random bit source
View Patent ↗Systems and methods of generating a highly random bit are provided. Two nearly uncoupled clocks are utilized to generate a near-random bit. Even/Odd sampling at a variable rate is provided to condition many near-random bits to yield a single bit with a value of one or zero 50% of the time.
1. A random number generator comprising a high entropy bit source, wherein the high entropy bit source generates a random number by:
obtaining a first clock signal using a clock source;
frequency dividing the first clock signal to generate a second clock signal using a frequency divider;
frequency multiplying and down modulating the second clock signal to generate a third clock signal using an analog frequency multiplier phase lock loop;
generating a random bit using the first clock signal and the third clock signal, wherein the random bit has a value selected from the group consisting of zero and one;
storing the random bit into a memory;
incrementing a bit counter for each stored random bit corresponding to a one;
bypassing the bit counter for each stored random bit corresponding to a zero; and
setting an output random bit to a one for each bit counter that corresponds to a predetermined value.
2. The random number generator of claim 1 wherein the clock source comprises a crystal oscillator.
3. The random number generator of claim 1 wherein the second clock signal is lower in frequency than the first clock signal.
4. The random number generator of claim 1 wherein the third clock signal is higher in frequency than the first and second clock signals.
5. The random number generator of claim 1 wherein the first clock signal and the third clock signal are statistically unrelated.
6. The random number generator of claim 1 wherein the first clock source is supplied to a latch to sample the third clock signal.
7. The random number generator of claim 1 wherein the third clock signal is supplied to read an output of a latch.
8. The random number generator of claim 1 wherein a processor monitors a total number of times the sampled bit is a one.
9. The random number generator of claim 8 wherein the processor sets the bit to a one based on the total number of times being an odd number.
10. The random number generator of claim 8 , wherein:
the memory is coupled to the high entropy bit source and the processor;
the memory stores a plurality of random bits generated using the high entropy bit source; and
the processor samples each random bit stored in the memory at least one time.
11. A method of generating a random number comprising:
obtaining a first clock signal using a single clock source;
frequency dividing the first clock signal to generate a second clock signal using a frequency divider;
frequency multiplying and down modulating the second clock signal to generate a third clock signal using an analog frequency multiplier phase lock loop;
generating a random bit using the first clock signal and the third clock signal, wherein the random bit has a value selected from the group consisting of zero and one;
storing the random bit into a memory;
incrementing a bit counter for each stored random bit corresponding to a one;
bypassing the bit counter for each stored random bit corresponding to a zero; and
setting an output random bit to a one for each bit counter that corresponds to a predetermined value.
12. The method of claim 11 wherein the predetermined value is an odd value.
13. The random number generator of claim 1 , wherein the clock source is used to synchronize an Ethernet transceiver.
14. The random number generator of claim 1 , wherein the first clock signal has a frequency of 25 MHz.
15. The random number generator of claim 1 , wherein the frequency divider divides a signal by a factor of 1.5.
16. The random number generator of claim 1 , wherein the second clock signal has a frequency of 16.67 MHz.
17. The random number generator of claim 1 , wherein the third clock signal has a frequency of 66 MHz.
18. The random number generator of claim 1 , wherein the analog frequency multiplier phase lock loop multiplies a signal by a factor of 4.
19. The random number generator of claim 1 , wherein the analog frequency multiplier phase lock loop performs down modulation.
20. The random number generator of claim 1 , wherein the high entropy bit source further comprises a second frequency divider and a fourth clock signal;
wherein the second frequency divider divides a signal by a factor of 2; and
wherein the fourth clock signal is derived by dividing the third clock signal using the second frequency divider.
21. The random number generator of claim 20 , wherein the high entropy bit source generates a random bit utilizing the first clock signal and the fourth clock signal.
22. The random number generator of claim 1 , wherein the random bit is generated based on a phase drift introduced by the analog frequency multiplier phase lock loop.