IP Library Patent Application 12383056
Patent Application
App. No. 12/383,056

Systems and methods for LDPC coded modulation

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Quick Facts
Patent No.
US None
App. No.
12/383,056
Abstract

Typical forward error correction methods employ Trellis Code Modulation. By substituting low density parity check coding in place of the convolution code as part of a combined modulation and encoding procedure, low density parity check coding and modulation can be performed. The low density parity check codes have no error floor, no cycles, an equal bit error rate for the information bits and the parity bits, and timely construction of both a parity check matrix with variable codeword size and a generator matrix is possible.

Claims (19)

1 - 12 . (canceled)

13 . A method of forward error correction coding of data bit signals using LDPC codes comprising:

determining at least one of a data rate and a latency; and

determining a LDPC generator matrix that encodes data bit signals.

14 . The method of claim 13 , wherein the at least one of a data rate and a latency are determined during an initialization or a configuration phase.

15 . The method of claim 13 , wherein the LDPC generator matrix is determined after the data rate and the latency have been determined.

16 . The method of claim 13 , wherein the LDPC code has a variable codeword length.

17 . The method of claim 16 , wherein the codeword length is varied depending on one or more of the data rate and the latency.

18 . The method of claim 13 , wherein the LDPC code does not have any cycles.

19 - 24 . (canceled)

25 . An information storage media comprising information that performs forward error correction coding of data bit signals using LDPC codes comprising:

information that determines at least one of a data rate and a latency; and

information that determines a LDPC generator matrix that encodes data bit signals.

26 . The media of claim 25 , wherein the at least one of a data rate and a latency are determined during an initialization or a configuration phase.

27 . The media of claim 25 , wherein the LDPC generator matrix is determined after the data rate and the latency have been determined.

28 . The media of claim 25 , wherein the LDPC code has a variable codeword length.

29 . The media of claim 28 , wherein the codeword length is varied depending on one or more of the data rate and the latency.

30 . The media of claim 25 , wherein the LDPC code does not have any cycles.

31 - 36 . (canceled)

Assignments (3)
AMENDED AND RESTATED INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Jan 4, 2021
From: TQ DELTA LLC
To: ALTER DOMUS (US) LLC
Reel/Frame 054898/0850 →
SECURITY INTEREST Recorded Oct 10, 2018
From: TQ DELTA, LLC
To: DLI LENDING AGENT, LLC
Reel/Frame 047212/0551 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2012
From: AWARE, INC.
To: TQ DELTA, LLC
Reel/Frame 029154/0937 →