Method and apparatus for performing predistortion
View Patent ↗Embodiments are described herein to provide better predistortion solutions for the linearization of high power amplifiers, especially those with memory effects. Many embodiments involve a method in which a predistorted signal z n is generated from input signal x n in accordance with z n = ∑ k = 1 K ∏ q = 1 Q P kq ( x n - q - 1 ) = P 11 ( x n ) P 12 ( x n - 1 ) … P 1 Q ( x n - Q - 1 ) + P 21 ( x n ) P 22 ( x n - 1 ) … P 2 Q ( x n - Q - 1 ) + … + P K 1 ( x n ) P K 2 ( x n - 1 ) … P KQ ( x n - Q - 1 ) for K terms and Q−1 delays, wherein each P kq is a complex valued function of a single complex variable. Also described are predistorter apparatus embodiments in which a predistorter includes complex multipliers for multiplying the value of each P kq having the same value of k to produce K products and at least one adder for adding the K products to generate predistorted signal z n from input signal x n in accordance with the equation above.
1. A method of performing predistortion comprising:
generating predistorted signal z n from input signal x n in accordance with
z
n
=
∑
k
=
1
K
∏
q
=
1
Q
P
kq
(
x
n
-
q
-
1
)
=
P
11
(
x
n
)
P
12
(
x
n
-
1
)
…
P
1
Q
(
x
n
-
Q
-
1
)
+
P
21
(
x
n
)
P
22
(
x
n
-
1
)
…
P
2
Q
(
x
n
-
Q
-
1
)
+
…
+
P
K
1
(
x
n
)
P
K
2
(
x
n
-
1
)
…
P
KQ
(
x
n
-
Q
-
1
)
for K terms and Q−1 delays, wherein each P kq is a complex valued function of a single complex variable.
2. The method as recited in claim 1 , further comprising:
using a polynomial to compute the value of at least one P kq .
3. The method as recited in claim 1 , further comprising:
using a look-up-table (LUT) to compute the value of at least one P kq .
4. The method as recited in claim 1 , wherein K=Q.
5. The method as recited in claim 4 , wherein
z
n
=
∑
k
=
1
Q
∏
q
=
1
Q
P
kq
(
x
n
-
q
-
1
)
=
x
n
P
11
(
x
n
)
P
12
(
x
n
-
1
)
…
P
1
Q
(
x
n
-
Q
-
1
)
+
x
n
-
1
P
21
(
x
n
)
P
22
(
x
n
-
1
)
…
P
2
Q
(
x
n
-
Q
-
1
)
+
…
+
x
n
-
Q
-
1
P
K
1
(
x
n
)
P
K
2
(
x
n
-
1
)
…
P
KQ
(
x
n
-
Q
-
1
)
.
6. The method as recited in claim 5 , wherein P kq is implemented as a function of the amplitude of x, where P kq =P kq (|x|).
7. The method as recited in claim 6 , wherein each P kq is computed using at least one of
a look-up-table (LUT) of one real variable |x|,
a polynomial of |x|,
a piecewise polynomial of |x|, or
an orthogonal polynomial of |x|.
8. The method as recited in claim 1 , wherein P kq is implemented as a function of the amplitude of x, where P kq =P kq (|x|).
9. The method as recited in claim 1 , wherein each P kq is computed using a look-up-table (LUT), wherein the entries of at least one of the LUTs is computed using an iterative least squares technique.
10. The method as recited in claim 1 , wherein P kq =1 for P kq for some k.
11. The method as recited in claim 1 , wherein generating predistorted signal z n from input signal x n comprises:
generating by a field-programmable gate array (FPGA) pre-distorted signal z n from input signal x n .
12. A predistorter comprising:
complex multipliers for multiplying the value of each P kq having the same value of k to produce K products;
at least one adder for adding the K products to generate predistorted signal z n from input signal x n in accordance with
z
n
=
∑
k
=
1
K
∏
q
=
1
Q
P
kq
(
x
n
-
q
-
1
)
=
P
11
(
x
n
)
P
12
(
x
n
-
1
)
…
P
1
Q
(
x
n
-
Q
-
1
)
+
P
21
(
x
n
)
P
22
(
x
n
-
1
)
…
P
2
Q
(
x
n
-
Q
-
1
)
+
…
+
P
K
1
(
x
n
)
P
K
2
(
x
n
-
1
)
…
P
KQ
(
x
n
-
Q
-
1
)
for K terms and Q−1 delays, wherein each P kq is a complex valued function of a single complex variable.
13. The predistorter as recited in claim 12 , wherein the predistorter comprises a field-programmable gate array (FPGA) upon which the complex multipliers and the at least one adder are realized.