IP Library Granted Patent US 8,017,425
Granted Patent B2
US 8,017,425 · App. 12/385,615 · Granted Sep 13, 2011

Method for fabricating an image sensor capable of increasing photosensitivity

Assignee: Crosstek Capital, LLC
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Quick Facts
Patent No.
US 8,017,425
App. No.
12/385,615
Granted
Sep 13, 2011
Kind
B2
Abstract

An image sensor capable of overcoming a decrease in photo sensitivity resulted from using a single crystal silicon substrate, and a method for fabricating the same are provided. An image sensor includes a single crystal silicon substrate, an amorphous silicon layer formed inside the substrate, a photodiode formed in the amorphous silicon layer, and a transfer gate formed over the substrate adjacent to the photodiode and transferring photoelectrons received from the photodiode.

Claims (35)

1. A method for fabricating an image sensor including a photodiode, the method comprising:

etching, with an etch mask, an opening in an epitaxial layer;

depositing an amorphous silicon layer into the opening; and

implanting ions in the amorphous silicon layer to form a P-region of amorphous silicon and an N-region of amorphous silicon;

wherein the etch mask includes a photoresist pattern; and

wherein the photodiode includes the P-region of amorphous silicon and the N-region of amorphous silicon.

2. The method of claim 1 , further comprising:

etching a trench in the epitaxial layer; and

depositing an oxide layer into the trench.

3. The method of claim 2 , further comprising:

planarizing the oxide layer to form a shallow trench isolation structure; and

aligning the amorphous silicon layer with the shallow trench isolation structure.

4. The method of claim 3 , wherein said planarizing the oxide layer comprises using a slurry including a polishing selectivity rate of silicon to silicon oxide between approximately 5:1 to approximately 30:1.

5. The method of claim 2 , wherein said planarizing the oxide layer is performed before said implanting ions in the amorphous silicon layer.

6. The method of claim 1 , further comprising forming a transfer gate adjacent to the photodiode.

7. The method of claim 6 , wherein said forming a transfer gate is performed before said implanting ions in the amorphous silicon layer.

8. The method of claim 1 , wherein the amorphous silicon layer comprises germanium.

9. The method of claim 1 , further comprising performing a heat diffusion process to form the photodiode.

10. The method of claim 1 , wherein the opening comprises a depth greater than the thickness of the photodiode.

11. The method of claim 1 , wherein the amorphous silicon layer is partially buried within the opening.

12. A method for fabricating an image sensor including a photodiode, the method comprising:

forming a trench in an epitaxial layer;

forming an insulation layer in the trench;

aligning the insulation layer with a surface of the epitaxial layer;

etching, with a first photoresist pattern, a portion of the epitaxial layer adjacent to the trench to form an opening;

depositing an amorphous silicon layer in the opening;

aligning the amorphous silicon layer with the top surface of the epitaxial layer; and

forming a P-region of amorphous silicon and an N-region of amorphous silicon in the amorphous silicon layer;

wherein the photodiode includes the P-region of amorphous silicon and the N-region of amorphous silicon.

13. The method of claim 12 , wherein the amorphous silicon layer comprises germanium.

14. The method of claim 12 , wherein said forming a P-region of amorphous silicon and an N-region of amorphous silicon comprises implanting ions in the amorphous silicon layer.

15. The method of claim 14 , wherein said forming a P-region of amorphous silicon and an N-region of amorphous silicon comprises performing a heat diffusion process.

16. The method of claim 12 , wherein said forming a trench in an epitaxial layer comprises using a second photoresist pattern.

17. The method of claim 12 , further comprising forming a transfer transistor before said forming a photodiode.

18. The method of claim 12 , wherein the amorphous silicon layer is partially buried within the opening.

Assignments (2)
MERGER Recorded Jul 22, 2011
From: CROSSTEK CAPITAL, LLC
To: INTELLECTUAL VENTURES II LLC
Reel/Frame 026637/0632 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: CROSSTEK CAPITAL, LLC
Reel/Frame 022834/0077 →
Priority Claims (1)
KR 2004-0115974 · Dec 30, 2004 · national
Continuity (2)
Continuation 11318638 · Dec 28, 2005
Related Publication 20090321736A1 · Dec 31, 2009