Biasing for transistor-based apparatuses and methods

1. An apparatus in a semiconductor body comprising:

a first transistor component having at least one gate terminal configured to receive an “on” gate signal to increase current flow through the first transistor component or an “off” gate signal to decrease the current flow through the first transistor component; and

a second transistor component having at least one gate terminal configured to receive an “on” gate signal to increase current flow through the second transistor component or an “off” gate signal to decrease the current flow through the second transistor component,

wherein the first transistor component and the second transistor component are connected in parallel to form a switching pair device,

wherein the transistor components are configured to operate together to equalize the current change per time through the switching pair device such that the total current through, or the transconductance of, the switching pair device approaches a constant value when the first and second transistor components are alternated between receiving the “on” and “off” gate signals,

wherein the first transistor component and the second transistor component each have a gate length attribute and a gate width attribute and at least one of the first or second transistor components includes a plurality of transistors connected in parallel, each transistor of the plurality of transistors having a gate width attribute and a gate, source, drain, and bulk terminal, and

wherein at least one of the plurality of transistors connected in parallel is “off” when another of the plurality of transistors connected in parallel is “on” and at least one of the plurality of transistors connected in parallel is “on” when another of the plurality of transistors connected in parallel is “off”.

2. An apparatus according to claim 1 , wherein the gate width attributes of the first transistor component and the second transistor component are equal, the gate length attributes for the first transistor component and the second transistor component are equal, the plurality of transistors each have equal gate width attributes, the sum of gate width attributes for each of the plurality of transistors equals the first transistor component gate width attribute.

3. An apparatus according to claim 1 , wherein the first and second transistor components are configured to receive a forward body-bias signal.

4. An apparatus according to claim 1 , further comprising:

a control circuit that controls the rising and falling amplitudes of each of the gate signals received by the first and second components and controls a bulk signal during switching such that the total current going through, or the transconductance of, the switching pair device approaches a constant value.

5. An apparatus according to claim 4 , wherein the control circuit is configured such that as the gate of the first transistor component receives the “off” gate signal, the first transistor component receives an “on” forward body-bias signal and as the gate of the first transistor component receives the “on” gate signal, the first transistor component receives an “off” forward body-bias signal.

6. An apparatus according to claim 4 , wherein the rising amplitude of the gate signal has a ramp rate that decreases as the gate signal approaches a preselected “on” gate signal value.

7. An apparatus according to claim 4 , wherein the falling amplitude of the gate signal has a ramp rate that increases as the gate signal approaches a preselected “off” gate signal value.

8. An apparatus according to claim 4 , wherein the control circuit comprises a plurality of inverting amplifiers that are configured to provide different driver strengths for the rising and falling amplitudes.

9. An apparatus according to claim 8 , wherein the plurality of inverting amplifiers controls the gate and bulk signals to maintain constant current through or transconductance established by the first and second transistor components when the gate signal is switching from “on” to “off” and the bulk signal is switching from “off” to “on” or when the gate signal is switching from “off” to “on” and the bulk signal is switching from “on” to “off”.

10. An apparatus in a semiconductor body comprising:

a first transistor component having at least one gate terminal configured to receive an “on” signal to increase current flow through the first transistor component or an “off” signal to decrease the current flow through the first transistor component; and

a second transistor component having at least one gate terminal configured to receive an “on” signal to increase current flow through the second transistor component or an “off” signal to decrease the current flow through the second transistor component,

wherein the first transistor component and the second transistor component are connected in parallel to form a switching pair device, the first and second transistor components configured to operate together to equalize a current change per time through the switching pair device such that a total current through the switching pair device approaches a constant value when the gate terminals of the first and second transistor components are alternated between receiving the “on” and “off” signals, at least one of the first transistor component and the second transistor component comprising a plurality of transistors connected in parallel, wherein at least one of the plurality of transistors connected in parallel is “off” if another of the plurality of transistors connected in parallel is “on” and at least one of the plurality of transistors connected in parallel is “on” if another of the plurality of transistors connected in parallel is “off,” and

wherein at least one of the first and second transistor components is configured to receive a forward body-bias signal.

11. A method for operating a switching pair device comprising:

alternately applying “on” and “off” control signals to a gate terminal of a first transistor component;

alternately applying “on” and “off” control signals to a gate terminal of a second transistor component, the “on” signal applied to the second transistor component such that the first and second transistor components do not receive an “on” signal simultaneously;

equalizing a current change per time through the switching pair device such that a total current through the switching pair device approaches a constant value when alternately applying the “on” and “off” control signals to the gate terminals of the first and second transistor components,

wherein at least one of the first transistor component and the second transistor component comprises a plurality of transistors connected in parallel and at least one of the plurality of transistors connected in parallel is “off” if another of the plurality of transistors connected in parallel is “on” and at least one of the plurality of transistors connected in parallel is “on” if another of the plurality of transistors connected in parallel is “off”; and

applying a forward body bias to at least one of the first and second transistor components.

12. A method for operating a multi-branch switching pair device comprising:

alternately applying “on” and “off” signals to each of a plurality of transistors of a first transistor component, the plurality of transistors coupled in parallel, at least one of the plurality of transistors of the first transistor component being “on” when another of the plurality of transistors of the first transistor component is “off” and at least one of the plurality of transistors of the first transistor component being “off” when another of the plurality of transistors of the first transistor component is “on;”

alternately applying “on” and “off” signals to each of a plurality of transistors of a second transistor component, the plurality of transistors coupled in parallel, at least one of the plurality of transistors of the second transistor component being “on” when another of the plurality of transistors of the second transistor component is “off” and at least one of the plurality of transistors of the second transistor component being “off” when another of the plurality of transistors of the second transistor component is “on;”

equalizing a current change per time through the multi-branch switching pair device such that a total current through the multi-branch switching pair device approaches a constant value when alternately applying the “on” and “off” signals to the plurality of transistors of the first and second transistor components;

applying a forward body bias to at least one of the transistors in the first or second transistor components.

13. A method according to claim 12 , further comprising:

determining which transistor of the at least one of the plurality of transistors of the first transistor component will receive an “on” signal when another transistor of the plurality of transistors of the first transistor component receives an “off” signal.

14. A method according to claim 13 , wherein the determination is based upon a mismatch characteristic between the at least one of the plurality of transistors of the first transistor component and another transistor of the plurality of transistors of the first transistor component.

15. A method according to claim 13 , wherein a first transistor of two most nearby matched transistors of the plurality of transistors of the first transistor component will receive an “on” control signal while a second transistor of the two most nearby matched transistors of the plurality of transistors of the first transistor component receives an “off” control signal.

16. A method according to claim 13 , wherein the determination is based upon a sequential predefined order of the physical layout of the plurality of transistors of the first transistor component.

17. A method according to claim 13 , wherein the determination is based on a random selection or pseudo random selection.