Minimizing adverse effects of skew between two analog-to-digital converters
View Patent ↗Skew between a first clock signal received by a first analog-to-digital converter (ADC) and a second clock signal received by a second ADC is adjusted to minimize error. Each ADC has an ADC element that produces a respective first or second digital output signal in response to an analog input signal and a respective first or second clock signal. A correction signal is produced in response to the first and second digital output signals. The skew between the first and second clock signals is then adjusted in response to the correction signal.
1. An analog-to-digital converter (ADC) system, comprising:
a first ADC comprising a first ADC element, the first ADC element producing a first digital output signal in response to a first analog signal representing an analog input signal to be converted and a first clock signal representing a master clock signal;
a second ADC comprising a second ADC element, the second ADC element producing a second digital output signal in response to a second analog signal representing the analog input signal to be converted and a second clock signal representing the master clock signal;
a correction estimator, the correction estimator comprising gain logic, offset logic, and a slope detector, the slope detector producing a slope factor representing a slope of the analog input signal, the gain logic producing a gain signal in response to the first digital output signal and the second digital output signal, the offset logic producing an offset signal in response to the first digital output signal and the second digital output signal, wherein the correction estimator applies the gain signal to at least one of the first digital output signal and the second digital output signal and applies the offset signal to at least one of the first digital output signal and the second digital output signal, and wherein the correction estimator produces a correction signal in response to the first digital output signal, the second digital output signal and the slope factor; and
a timing adjuster, the timing adjuster adjusting a skew between the first clock signal and the second clock signal in response to the correction signal.
2. The ADC system claimed in claim 1 , wherein the correction estimator comprises:
a subtractor coupled to an output of one of the first ADC element and second ADC element;
a multiplier coupled to an output of one of the first ADC element and second ADC element, the multiplier receiving the gain signal; and
an adder coupled to an output of one of the first ADC element and second ADC element, the adder receiving the offset signal.
3. The ADC system claimed in claim 2 , wherein:
the multiplier and the adder together define a skew estimator, and an input of the skew estimator is coupled to an output of one of the first ADC element and second ADC element; and
a first input of the subtractor is coupled to an output of the skew estimator, a second input of the subtractor is coupled to an output of an other one of the first ADC element and second ADC element.
4. The ADC system claimed in claim 3 , wherein:
the subtractor produces an error signal; and
the correction estimator produces the correction signal, the offset signal, and the gain signal in response to the error signal.
5. The ADC system claimed in claim 1 , wherein the slope detector comprises:
a delay system, the delay system producing a plurality of samples of the analog input signal delayed by different amounts from each other; and
a comparator system, the comparator system comparing the plurality of samples of the analog input signal with a sample of one of the first and second analog signals to determine whether the analog input signal is rising or falling.
6. The ADC system claimed in claim 1 , wherein the correction estimator comprises a digital signal processor.
7. An analog-to-digital converter (ADC) system, comprising:
a first ADC comprising a first ADC element, the first ADC element producing a first digital output signal in response to a first analog signal representing an analog input signal to be converted and a first clock signal representing a master clock signal;
a second ADC comprising a second ADC element, the second ADC element producing a second digital output signal in response to a second analog signal representing the analog input signal to be converted and a second clock signal representing the master clock signal;
a slope detector for producing a slope factor representing a slope of the input analog signal, the slope detector comprising a delay system and a comparator system, the delay system producing a plurality of samples of the analog input signal delayed by different amounts from each other, the comparator system comparing the plurality of samples of the analog input signal with the first analog signal;
a correction estimator, the correction estimator comprising gain logic for producing a gain signal, offset logic for producing an offset signal, and correction logic for producing a correction signal, the correction estimator further comprising a subtractor, an adder and a multiplier, the subtractor producing an error signal in response to a skew estimate and an output of one of the first ADC and second ADC, the adder adding the offset signal to an output of the multiplier to produce the skew estimate, and the multiplier multiplying an output of an other one of the first ADC and second ADC by the gain signal, wherein the offset logic produces the offset signal in response to a previous offset signal value and previous error signal value and produces the gain signal in response to a previous gain signal value, a previous error signal value and a previous sampled value; and
a timing adjuster, the timing adjuster adjusting a skew between the first clock signal and the second clock signal in response to the correction signal.
8. The ADC system claimed in claim 7 , wherein:
the first ADC comprises a first delay element, the first delay element delaying the signal to be converted by a predetermined amount to produce the first analog signal;
the second ADC comprises a second delay element, the second delay element delaying the signal to be converted by a predetermined amount to produce the second analog signal;
the comparator system comprises a third delay element, a fourth delay element, a first comparator, a second comparator, and slope detection logic, the first comparator receiving an output of the third delay element, the second comparator receiving an output of the fourth delay element, the third delay element delaying the signal to be converted by an amount less than the predetermined amount to produce a third analog signal, and the fourth delay element delaying the signal to be converted by an amount greater than the predetermined amount to produce a fourth analog signal, the first comparator comparing the third analog signal with the first analog signal to produce a first comparator output, the second comparator comparing the fourth analog signal with the first analog signal to produce a second comparator output, the slope detection logic producing the slope factor in response to the first comparator output and the second comparator output.
9. A method of operation of a system comprising a first analog-to-digital converter (ADC) having a first ADC element and a second ADC having a second ADC element, the method comprising:
the first ADC element producing a first digital output signal in response to a first analog signal representing an analog input signal to be converted and a first clock signal representing a master clock signal;
the second ADC element producing a second digital output signal in response to a second analog signal representing the analog input signal to be converted and a second clock signal representing the master clock signal;
producing a correction signal by producing a gain signal and an offset signal in response to the first digital output signal and the second digital output signal, producing a slope factor representing a slope of the analog input signal, applying the gain signal to at least one of the first digital output signal and the second digital output signal, and applying the offset signal to at least one of the first digital output signal and the second digital output signal, wherein the correction signal is produced in response to the first digital output signal, the second digital output signal and the slope factor; and
adjusting a skew between the first clock signal and the second clock signal in response to the correction signal.
10. The method claimed in claim 9 , wherein producing a correction signal comprises:
determining an error signal by determining a difference between a skew estimate and a signal received from an output of one of the first ADC element and second ADC element;
multiplying a signal received from an output of one of the first ADC element and second ADC element by a gain signal to produce a gain-multiplied signal; and
adding an offset signal to the gain-multiplied signal;
wherein the correction signal is produced in response to the error signal.
11. The method claimed in claim 9 , wherein producing a slope factor comprises:
producing a plurality of samples of the analog input signal delayed by different amounts from each other; and
comparing the plurality of samples of the analog input signal with a sample of one of the first and second analog signals to determine whether the analog input signal is rising or falling.