IP Library Granted Patent US 8,114,787
Granted Patent B2
US 8,114,787 · App. 12/389,236 · Granted Feb 14, 2012

Integrated circuit nanowires

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Quick Facts
Patent No.
US 8,114,787
App. No.
12/389,236
Granted
Feb 14, 2012
Kind
B2
Abstract

Implementations of encapsulated nanowires are disclosed.

Claims (15)

1. A method for producing encapsulated nanowires, comprising:

providing a substrate having a surface layer;

patterning the surface layer to form nanometer-sized features;

disposing a conductive material in the nanometer-sized features using a metal precursor conveyed in a supercritical carbon dioxide to form nanowires on the substrate;

removing the surface layer; and

forming one or more insulating monolayers to entirely encapsulate the nanowires, wherein forming each of the one or more insulating monolayers includes disposing a self-assembled monolayer (SAM) including octadecylsiloxane (ODS) at a temperature of less than about 350° C. and oxidizing the ODS by an exposure of ultraviolet radiation.

2. The method of claim 1 , wherein the surface layer comprises a photoresist layer and wherein patterning the surface layer comprises performing lithography to pattern the photoresist layer.

3. The method of claim 2 , wherein performing lithography comprises performing one of nanoimprint lithography, electron beam lithography or extreme ultraviolet photolithography.

4. The method of claim 1 , wherein the insulating material comprises silicon dioxide.

5. The method of claim 1 , wherein the conductive material comprises copper, aluminum, tungsten, or any combination thereof.

6. The method of claim 1 , wherein the surface layer comprises a stressed silicon dioxide layer and wherein patterning the surface layer comprises forming nanometer-sized cracks in the stressed silicon dioxide layer.

7. The method of claim 6 , further comprising:

patterning the substrate prior to disposing the surface layer on the substrate.

8. The method of claim 6 , wherein disposing the conductive material in the nanometer-sized features comprises disposing the metal in the nanometer-sized cracks.

9. The method of claim 1 , wherein disposing the conductive material in the nanometer-sized features comprises disposing the conductive material in the nanometer-sized features at temperatures of less than about 350° C.

Assignments (4)
SECURITY INTEREST Recorded Jan 29, 2019
From: EMPIRE TECHNOLOGY DEVELOPMENT LLC
To: CRESTLINE DIRECT FINANCE, L.P.
Reel/Frame 048373/0217 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2011
From: KRUGLICK, EZEKIEL
To: ARDENT RESEARCH CORPORATION
Reel/Frame 027202/0492 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2011
From: ARDENT RESEARCH CORPORATION
To: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Reel/Frame 027202/0513 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2009
From: KRUGLICK, EZEKIEL
To: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Reel/Frame 023161/0853 →