Semiconductor device, manufacturing method of semiconductor device, semiconductor manufacturing and inspecting apparatus, and inspecting apparatus
View Patent ↗A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.
1. A semiconductor device comprising: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; and at least one layer of Cu wiring provided in the insulating layer via an composite layer including a barrier layer and a seed layer on the barrier layer and provided between the Cu wiring and the insulating layer, wherein
the barrier layer includes Ta crystal;
the seed layer includes an alloy crystal layer of Cu and Al;
the Cu wiring is formed such that 60% or higher of all grain boundaries configuring crystals of the Cu wiring are coincidence boundaries of Sigma value 27 or less in at least one cross section of the Cu wiring and that a total value of orientations of a (111) plane and a (200) plane in the Cu wiring is 94%;
the orientation of the (111) plane of Cu wiring is 93% and the orientation of the (200) plane is 1%; and
the barrier layer comprises a single layer of Ta crystal, or a composite layer of Ta crystal and TaN crystal.
2. A semiconductor device comprising: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; and at least one layer of Cu wiring provided in the insulating layer via an composite layer including a barrier layer and a seed layer on the barrier layer and provided between the Cu wiring and the insulating layer, wherein
the barrier layer includes Ru crystal;
the seed layer includes an alloy crystal layer of Cu and Al;
the Cu wiring is formed such that 40% or higher of all grain boundaries configuring crystals of the Cu wiring are twin boundaries of Sigma value 3 in at least one cross section of the Cu wiring and that a total value of orientations of a (111) plane and a (200) plane in the Cu wiring is 98%;
the orientation of the (111) plane of the Cu wiring is 44% and the orientation of the (200) plane is 54%; and
the barrier layer comprises a single layer of Ru crystal, or a composite layer of Ru crystal and RuN crystal.