Microprocessor performance improvement by dynamic NBTI compensation through transistor forward biasing
View Patent ↗A method for compensating negative bias temperature instability (NBTI) effects on a given model of transistors includes monitoring the NBTI effects on the transistors over time, determining a change in a threshold voltage of the transistors over time based on the monitoring, determining a forward bias voltage based on the change in threshold voltage, and applying the forward bias voltage to the transistors over time. The method may further include storing the monitoring results in a lookup table, and adjusting the forward bias voltage based on the lookup table. The monitoring may include emulating the NBTI effects on a system comprising a plurality of semiconductor devices in which the transistors are used.
1. A method for compensating negative bias temperature instability (NBTI) effects on a given model of PMOS transistors in a processor, the method comprising:
monitoring a plurality of threshold voltage shifts of the PMOS transistors on an emulated time scale under accelerated stress conditions to emulate the effects of NTBI degradation of the PMOS transistors over an actual lifetime of the PMOS transistors;
extrapolating a plurality of expected threshold voltage shifts of the PMOS transistors corresponding to normal operating conditions over the lifetime of the PMOS transistors based on the monitoring;
determining a plurality of forward bias voltages for the PMOS transistors based on the plurality of expected threshold voltage shifts, wherein each forward bias voltage is sufficient to compensate for the corresponding one expected threshold voltage shift;
storing the plurality of forward bias voltages for the PMOS transistors in a lookup table accessible by the processor; and
during runtime, applying a selected forward bias voltage to the PMOS transistors, wherein the selected forward bias voltage is one of the plurality of forward bias voltages stored in the lookup table that corresponds to a time in the lifetime of the PMOS transistors corresponding to the runtime.
2. The method according to claim 1 , further comprising:
adjusting the forward bias voltage based on the lookup table.
3. The method according to claim 2 , wherein the monitoring includes emulating the NBTI effects on a system comprising a plurality of semiconductor devices in which PMOS transistors are used.
4. The method according to claim 3 , wherein the same lookup table is used to adjust the forward bias voltage on PMOS transistors in the plurality of semiconductor devices.
5. The method according to claim 1 , further comprising:
monitoring an integrated circuit quiescent current (IDDQ) of the PMOS transistors; and
adjusting the forward bias voltage on the transistors such that the IDDQ of the PMOS transistors is maintained at a predefined level.
6. A non-transistory computer-readable medium comprising instructions for causing a computer to compensate NBTI effects on a given model of PMOS transistors in a processor by performing:
monitoring a plurality of threshold voltage shifts of the PMOS transistors on an emulated time scale under accelerated stress conditions to emulate the effects of NTBI degradation of the PMOS transistors over an actual lifetime of the PMOS transistors;
extrapolating a plurality of expected threshold voltage shifts of the PMOS transistors corresponding to normal operating conditions over the lifetime of the PMOS transistors based on the monitoring;
determining a plurality of forward bias voltages for the PMOS transistors based on the plurality of expected threshold voltage shifts, wherein each forward bias voltage is sufficient to compensate for the corresponding one expected threshold voltage shift;
storing the plurality of forward bias voltages for the PMOS transistors in a lookup table accessible by the processor; and
during runtime, applying a selected forward bias voltage to the PMOS transistors, wherein the selected forward bias voltage is one of the plurality of forward bias voltages stored in the lookup table that corresponds to a time in the lifetime of the PMOS transistors corresponding to the runtime.
7. The computer-readable medium according to claim 6 , further comprising instructions for causing the computer to perform:
adjusting the forward bias voltage based on the lookup table.
8. The computer-readable medium according to claim 7 , wherein the monitoring includes emulating the NBTI effects on a system comprising a plurality of semiconductor devices in which PMOS transistors are used.
9. The computer-readable medium according to claim 8 , wherein the same lookup table is used to adjust the forward bias voltage on the PMOS transistors in the plurality of semiconductor devices.
10. The computer-readable medium according to claim 6 , further comprising instructions for causing the computer to perform:
monitoring an integrated circuit quiescent current (IDDQ) of the PMOS transistors; and
adjusting the forward bias voltage on the transistors such that the IDDQ of the PMOS transistors is maintained at a predefined level.
11. A computer system comprising:
memory;
a processor operatively connected to the memory; and
computer-readable instructions stored in the memory for causing the processor to perform:
monitoring a plurality of threshold voltage shifts of the PMOS transistors on an emulated time scale under accelerated stress conditions to emulate the effects of NTBI degradation of the PMOS transistors over an actual lifetime of the PMOS transistors;
extrapolating a plurality of expected threshold voltage shifts of the PMOS transistors corresponding to normal operating conditions over the lifetime of the PMOS transistors based on the monitoring;
determining a plurality of forward bias voltages for the PMOS transistors based on the plurality of expected threshold voltage shifts, wherein each forward bias voltage is sufficient to compensate for the corresponding one expected threshold voltage shift;
storing the plurality of forward bias voltages for the PMOS transistors in a lookup table accessible by the processor; and
during runtime, applying a selected forward bias voltage to the PMOS transistors, wherein the selected forward bias voltage is one of the plurality of forward bias voltages stored in the lookup table that corresponds to a time in the lifetime of the PMOS transistors corresponding to the runtime.
12. The computer system according to claim 11 , further comprising instructions for causing the processor to perform:
adjusting the forward bias voltage based on the lookup table.
13. The computer system according to claim 12 , wherein the monitoring includes emulating the NBTI effects on a system comprising a plurality of semiconductor devices in which PMOS transistors are used.
14. The computer system according to claim 13 , wherein the same lookup table is used to adjust the forward bias voltage on the PMOS transistors in the plurality of semiconductor devices.
15. The computer system according to claim 11 , further comprising instructions for causing the processor to perform:
monitoring an integrated circuit quiescent current (IDDQ) of the PMOS transistors; and
adjusting the forward bias voltage on the transistors such that the IDDQ of the PMOS transistors is maintained at a predefined level.