Method of manufacturing an electronic device including a PNP bipolar transistor

1. A method of manufacturing an electronic device including a PNP bipolar transistor, the method comprising:

forming a collector in a substrate;

depositing a base layer and an emitter layer on the substrate; and

growing a nitride interface layer on the base layer as a base current modulator, with the nitride interface layer arranged between the base layer and the emitter layer;

wherein the step of growing the nitride interface layer is carried out in a mixture of NH 3 , N 2 , H 2 and O 2 .

2. The method of claim 1 , wherein the step of growing the nitride interface layer takes place at a temperature of from 450° C. to 900° C.

3. The method of claim 1 , wherein the nitride interface layer has a thickness of between 2 Å and 12 Å.

4. A method of manufacturing an electronic device including a PNP bipolar transistor, the method comprising:

forming a P-well in a substrate to define a collector of the PNP bipolar transistor;

forming a base layer epitaxially on the substrate above a portion of the P-well, a central region of the base layer being formed of an N-type crystalline material and a peripheral region being formed of a polycrystalline material;

forming a nitride interface layer over a part of the central region of the base layer;

forming an oxide layer adjacent to and surrounding the nitride interface layer over a remainder of the central region of the base layer not covered by the nitride interface layer;

forming a nitride layer over the entirety of the oxide layer;

forming a P-type layer over the nitride interface layer and the nitride layer to define an emitter of the PNP bipolar transistor; and

forming sidewall spacers on edges of a stack comprising the oxide layer, the nitride layer and the P-type layer, the sidewall spacers extending from an uppermost surface of the P-type layer to a top surface in the peripheral region, leaving a portion of the top surface in the peripheral region exposed;

whereby the P-type layer defining the emitter is spaced by the nitride interface layer from the base layer in a central portion and is spaced by the stack from the base layer in a peripheral portion.

5. The method of claim 4 , wherein the nitride interface layer is formed to a thickness of around 2-12 Angstroms.

6. The method of claim 5 , wherein the nitride interface is formed by growing the nitride interface layer in a pure NH 3 environment.

7. The method of claim 5 , wherein the nitride interface layer comprises a mixture of nitride and oxide.