Semiconductor integrated circuit device
View Patent ↗A semiconductor integrated circuit device including a dummy via is disclosed. In the semiconductor integrated circuit device, problems such as reduction in the designability and increase in fabrication cost which result from the existence of a dummy wire connected to the dummy via are suppressed. The semiconductor integrated circuit device includes a substrate and three or more wiring layers formed on the substrate. The dummy via connects between a first wiring layer and a second wiring layer. The dummy wire connected to the dummy via exists in the second wiring layer. A protrusion amount of the dummy wire is smaller than a protrusion amount of an intermediate wire included in a stacked via structure.
1. A semiconductor integrated circuit device, comprising:
a substrate;
three or more wiring layers on the substrate;
a dummy via between adjacent first and second wiring layers of the three or more wiring layers;
a dummy wire formed in the second wiring layer and connected to the dummy via; and
one or more stacked via structures formed in the three or more wiring layers, each of the one or more stacked via structures including an intermediate wire in the second wiring layer, a first via between the first wiring layer and the second wiring layer, and a second via between the second wiring layer and a third wiring layer, the first via and the second via being connected to the intermediate wire, the first via and the second via at least partially overlapping with one another in plan view,
wherein a protrusion amount of the dummy wire is smaller than a protrusion amount of the intermediate wire in any of the stacked via structures.
2. The semiconductor integrated circuit device of claim 1 , wherein the protrusion amount of the dummy wire is substantially equal to a wire end side protrusion amount of a wire formed in a top or bottom layer of any one of the stacked via structures.
3. The semiconductor integrated circuit device of claim 1 , wherein the second wiring layer in which the dummy wire is formed is above the dummy via.
4. The semiconductor integrated circuit device of claim 1 , wherein the second wiring layer in which the dummy wire is formed is below the dummy via.
5. The semiconductor integrated circuit device of claim 1 , wherein the dummy via is connected to a wire which is included in any one of the stacked via structures and which is formed in the first wiring layer.
6. The semiconductor integrated circuit device of claim 1 , wherein the dummy via has a smaller cross-sectional area than any via included in the stacked via structures.
7. The semiconductor integrated circuit device of claim 1 , wherein the dummy via connected to the dummy wire includes two or more dummy vias.
8. The semiconductor integrated circuit device of claim 1 , wherein a protrusion amount of the dummy wire is a longer one of two averages of distances from via ends to wire ends respectively along two orthogonal directions along which the dummy wire extends.