Provided is an image sensor that may reduce the number of external terminals for downsizing of a chip, generate a write signal (RE) of a Y address with one pulse, and employ an external circuit having the same configuration as that of the conventional example. The image sensor uses an X-Y address scanning system in a pixel element matrix, and includes: a register latch that sets a Y address for selection of a row according to a write signal; a Y address register that decodes a Y address data from the register latch to output a Y address signal for selection of the row in the pixel element matrix; and an X address control unit that generates an X address signal for selection of a column. The register latch brings the Y address register into a disenable state so as to cause the Y address register not to output the Y address signal at timing at which the write signal is input to the Y address register, and brings the Y address register into an enable state so as to cause the Y address register to output the Y address signal at timing at which the input of the write signal is completed and the Y address data is written into the Y address register.
1. An image sensor comprising a matrix of pixel elements for storing pixel data each addressable by an X-Y address scanning system, comprising:
a register latch responsive to a pulse of write signal to turn off a Y address scanning enable signal no earlier than a leading edge of the write signal pulse and turn on the Y address scanning enable signal no earlier than a trailing edge of the write signal pulse, the register latch configured to read and hold Y address data substantially simultaneously with the leading edge of the write signal pulse; and
a Y address register configured to disable itself from addressing the pixel elements while the Y address scanning enable signal from the register latch is turned off and decodes the Y address data held by the register latch.
2. The image sensor according to claim 1 , wherein the resister latch turns off the Y address scanning enable signal substantially simultaneously with the leading edge of the write signal pulse, whereas turning on the Y address scanning enable signal subsequently to the training edge of the write signal pulse.
3. The image sensor according to claim 1 , wherein the Y address register selects a row of pixel elements, using the decoded Y address data, when the Y address scanning enable signal is turned on.
4. The image sensor according to claim 3 , further comprising an X address control unit configured to increment an X address signal to sequentially select the columns of pixel elements.
5. The image sensor according to claim 4 , further comprising switches each functioning to gate outputs of a column of pixel elements, and the X address signal from the X address control unit, while being incremented, selectively activates the switches to sequentially enable outputs from the columns of pixel elements.