IP Library Granted Patent US 7,863,752
Granted Patent B2
US 7,863,752 · App. 12/392,947 · Granted Jan 4, 2011

MEMS device with integrated via and spacer

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Quick Facts
Patent No.
US 7,863,752
App. No.
12/392,947
Granted
Jan 4, 2011
Kind
B2
Abstract

A MEMS device and fabrication method are disclosed. A bottom substrate having an insulating layer sandwiched between an upper layer and a lower layer may be bonded to a device layer. One or more portions of the upper layer may be selectively removed to form one or more device cavities. Conductive vias may be formed through the lower layer at locations that underlie the one or more device cavities and electrically isolated from the lower layer. Devices may be formed from the device layer. Each device overlies a corresponding device cavity. Each device may be connected to the rest of the device layer by one or more corresponding hinges formed from the device layer. One or more electrical contacts may be formed on a back side of the lower layer. Each contact is electrically connected to a corresponding conductive via.

Claims (29)

1. A method for fabricating a microelectromechanical system (MEMS) device, comprising:

a) forming one or more conductive vias through a lower layer of a bottom substrate having an insulating layer sandwiched between an upper layer and the lower layer, wherein each of the vias is electrically isolated from the lower layer;

b) electrically connecting the vias to one or more corresponding electrical contacts formed on a back side of the lower layer;

c) selectively removing one or more portions of the upper layer that overlie the one or more vias to form one or more device cavities;

d) bonding a device layer to the bottom substrate; and

e) forming one or more devices from the device layer, wherein each of the one or more devices overlies a corresponding one of the one or more device cavities, and wherein each of the one or more devices is connected to the rest of the device layer by one or more corresponding hinges, wherein each hinge is formed from the device layer, and wherein each of the one or more devices is electrically isolated from the one or more vias.

2. The method of claim 1 wherein the bottom substrate is a silicon on insulator substrate.

3. The method of claim 1 wherein e) includes removing selected portions of the device layer to form the one or more devices and one or more hinges.

4. The method of claim 1 wherein the one or more devices include one or more mirrors.

5. The method of claim 1 wherein c) includes protecting the back side of the lower layer during removal of the selected portions of the upper layer.

6. The method of claim 1 wherein d) includes a high-temperature bonding process.

7. The method of claim 1 wherein d) includes a low-temperature bonding process.

8. The method of claim 1 , further comprising, after c) and before b), forming one or more device electrodes in the one or more device cavities, wherein each device electrode is electrically connected to a corresponding one of the one or more vias.

9. The method of claim 8 wherein the one or more device electrodes are formed on one more portions of the insulating layer exposed by removal of the one or more portions of the upper layer.

10. The method of claim 1 wherein the device layer is a layer of a top substrate having an insulator layer sandwiched between the device layer and an additional layer.

11. The method of claim 10 , further comprising removing the additional layer prior to e).

12. The method of claim 11 , further comprising: after d) disposing an electrically conductive bonding material on the electrical contacts formed on a back side of the lower layer.

13. The method of claim 12 , further comprising: before d) disposing an electrically conductive bonding material on the electrical contacts formed on a back side of the lower layer.

14. A microelectromechanical system (MEMS) device, comprising:

a) a bottom substrate having an insulating layer sandwiched between an upper layer and a lower layer, wherein one or more portions of the upper layer have been selectively removed to form one or more device cavities;

b) one or more conductive vias formed through the lower layer at locations that underlie the one or more device cavities, wherein each of the vias is electrically isolated from the lower layer;

c) one or more electrical contacts formed on a back side of the lower layer, wherein each of the one or more electrical contacts is electrically connected to a corresponding one of the one or more conductive vias;

d) a device layer bonded to the bottom substrate; and

e) one or more devices formed from the device layer, wherein each of the one or more devices overlies a corresponding one of the one or more device cavities, and wherein each of the one or more devices is connected to the rest of the device layer by one or more corresponding hinges, wherein each hinge is formed from the device layer.

15. The device of claim 14 wherein the bottom substrate is a silicon on insulator substrate.

16. The device of claim 14 wherein selected portions of the device layer have been removed to form the one or more devices and one or more hinges.

17. The device of claim 14 wherein the one or more devices include one or more mirrors.

18. The device of claim 14 , further comprising one or more device electrodes formed in the one or more device cavities, wherein each device electrode is electrically connected to a corresponding one of the one or more vias.

19. The device of claim 18 wherein the one or more device electrodes are formed on one more portions of the insulating layer that are exposed by removal of the one or more portions of the upper layer.

Assignments (5)
SECURITY AGREEMENT Recorded Jan 8, 2014
From: CAPELLA PHOTONICS, INC.
To: DBD CREDIT FUNDING LLC; C/O FORTRESS INVESTMENT GROUP LLC
Reel/Frame 031947/0056 →
RELEASE Recorded Aug 21, 2012
From: SILICON VALLEY BANK
To: CAPELLA PHOTONICS, INC.
Reel/Frame 028824/0690 →
SECURITY AGREEMENT Recorded Jul 9, 2009
From: CAPELLA PHONTONICS, INC.
To: TEATON CAPITAL COMPANY; SAND HILL FINANCIAL COMPANY; FORMATIVE VENTURES EMERGING TECHNOLOGIES FUND, LP
Reel/Frame 022932/0669 →
SECURITY AGREEMENT Recorded May 5, 2009
From: CAPELLA PHOTONICS, INC.
To: SILICON VALLEY BANK; BINGHAM, RAYMOND H.; BLACK DIAMOND VENTURES XIV, LLC.; DONALD L. LUCAS, SUCC TTEE DONALD L. LUCAS PROFIT SHARING TRUST DTD 1/1/84; DONALD L. LUCAS, TTEE DONALD L. AND LYGIA LUCAS TRUST DTD 12/3/84; LUCAS VENTURE GROUP I, LLC; THE LUCAS BROTHERS FOUNDATION; BRENDAN JOSEPH CASSIN AND ISABEL B. CASSIN, TRUSTEES OF THE CASSIN FAMILY TRUST U/D/T DATED 1/31/96; CASSIN FAMILY PARTNERS, A CALIFORNIA LIMITED PARTNERSHIP; ROBERT S. CASSIN CHARITABLE TRUST UTA DATED 2/20/97; LEVENSOHN VENTURE PARTNERS III ANNEX FUND, L.P.; LEVENSOHN VENTURE PARTNERS III, L.P.; LVP III ASSOCIATES FUND, L.P.; SAINTS CAPITAL FALCON, L.P.; RUSTIC CANYON VENTURES, SBIC, LP; ZACCARIA, BERT L.; BRENDAN JOSEPH CASSIN, TRUSTEES OF THE CASSIN 1997 CHARITABLE TRUST UTA DATED 1/28/97
Reel/Frame 022641/0593 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2009
From: OSTROM, ROBERT
To: CAPELLA PHOTONICS, INC.
Reel/Frame 022313/0325 →