Electrostatic discharge protection of a capacitive type fingerprint sensing array
View Patent ↗A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes a first capacitor plate placed vertically under the upper surface of a dielectric layer and a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate. Electrostatic discharge protection relative to electrostatic potential that may be carried by an ungrounded fingertip is provided by placing a number of grounded metal paths within the dielectric layer to spatially surround each of the first and second capacitor plates, this being done in a manner that does not disturb the ungrounded state of the fingertip.
1. A fingerprint sensing circuit, comprising:
a plurality of sensing cells arranged in a 2-dimensional grid array, each cell having at least two plates for forming capacitors, the plates lying generally in a single plane;
a dielectric layer in which said at least two plates are disposed, the dielectric layer having an upper surface above the plane of the plates and a lower surface below the plane of the plates; and
a conductive path forming a planar 2-dimensional grid and positioned:
within said dielectric layer;
generally in the plane of the plurality of sensing cells;
in between adjacent ones of the sensing cells; and
in between each of the at least two plates;
the conductive path being coupled to ground potential to provide electro-static discharge protection for the sensing cell.
2. A fingerprint sensing circuit, comprising:
a dielectric layer having an upper and a lower surface;
a two-dimensional array of capacitive sensor cells formed within said dielectric layer, said array arranged in a plurality of rows and a plurality of columns and wherein:
each said row of sensor cells is spaced apart from adjacent rows of sensor cells, and top and bottom rows are spaced apart from the top and bottom of the array, respectively, by a spacer row;
each said column of sensor cells is spaced apart from adjacent columns of sensor cells, and columns at lateral edges of the array are spaced apart from said lateral edges, by a spacer column; and
each sensor cell is comprised of at least a first capacitor plate disposed in a first plane within said dielectric layer;
a grounding grid comprising a plurality of electrically interconnected rows and columns of conductive grid members disposed in a single plane within said dielectric layer, each said spacer row containing a row conductive grid member and each said spacer column containing a column conductive grid member, such that each sensor cell is fully surrounded by but physically and electrically isolated from conductive grid members;
wherein said first capacitor plates and said conductive grid members are generally co-planar in a first plane above the lower surface of the dielectric layer and below the upper surface of the dielectric layer; and
wherein said grounding grid is electrically coupled to ground potential to provide electrostatic discharge protection for each sensor cell.
3. The circuit according to claim 2 , further comprising:
each sensor cell including a second capacitor plate spaced apart from said first capacitor plate by a spacing region; and
said grounding grid further including conductive members disposed in each said spacing region between said first and second capacitor plates of each said sensor cell such that said conductive members in said spacing regions are physically and electrically isolated from said first and second capacitor plates.