High-voltage integrated circuit device including high-voltage resistant diode

1. A high-voltage integrated circuit device comprising:

a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage;

a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage;

a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region;

a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region;

a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region;

a high-voltage metal oxide semiconductor transistor formed between the low-voltage circuit region and the high-voltage circuit region; and

a third isolation region surrounding the high-voltage metal oxide semiconductor transistor to isolate the high-voltage metal oxide semiconductor transistor from the low-voltage circuit region and the high-voltage circuit region and having a portion overlapping the high-voltage metal oxide semiconductor transistor.

2. The device of claim 1 , wherein the third isolation region comprises:

a first conductive type substrate;

a first conductive type epitaxial layer formed on the substrate;

a first diffusion region of a first conductive type, which overlaps the substrate and the epitaxial layer; and

a second diffusion region of the first conductive type, which overlaps the substrate and the epitaxial layer and is separated by a predetermined distance from the first diffusion region.

3. The device of claim 1 , wherein the high-voltage metal oxide semiconductor transistor comprises:

a first conductive type well region formed in the first diffusion region;

a second conductive type and heavily doped source region formed in an upper region of the well region;

a first conductive type and heavily doped contact region formed in the upper region of the well region to be adjacent to the source region;

a source electrode electrically connected to the source region and the contact region; and

a first conductive type top region formed in the epitaxial layer and between the first diffusion region and the second diffusion region;

a gate insulating film formed on the top region;

a gate electrode formed on the gate insulating film;

a second conductive type and heavily doped drain region formed in an upper region of the epitaxial layer and between the top region and the second diffusion region; and

a drain electrode electrically connected to the drain region.

4. The device of claim 2 , wherein the first diffusion region comprises:

a first conductive buried layer overlapping the substrate and the epitaxial layer; and

a first conductive type impurity layer formed on and connected to the first conductive buried layer.

5. The device of claim 2 , wherein the second diffusion region comprises:

another first conductive type buried layer overlapping the substrate and the epitaxial layer; and

another first conductive type impurity layer formed on and connected to the another first conductive type buried layer.