Technique to improve dropout in low-dropout regulators by drive adjustment
View Patent ↗An electronic device includes a low drop-out regulator for providing a regulated output voltage. The low drop-out regulator generally comprises a power MOSFET transistor having a gate coupled to a driver. The driver has a first path including an NMOS transistor and being coupled to the gate of the power MOSFET, a second path having a PMOS transistor and being coupled to the gate of the power MOSFET, and a switch for alternately switching between the first and second paths so as to provide a voltage to the gate of the power MOSFET ranging from ground to a power supply level.
1. An apparatus for providing an output current and an output voltage to a load, the apparatus comprising:
a power transistor that is adapted to be coupled to a load;
a measuring circuit that is coupled to the power transistor, wherein the measuring circuit generates a feedback voltage;
an error amplifier that is coupled to the measuring circuit, wherein the error amplifier compares the feedback voltage to a reference voltage;
an NMOS transistor that is coupled to the error amplifier at its gate and that is coupled to the control electrode at its source on a switching node;
a PMOS transistor that is coupled to the switching node at its source and that is coupled to the error amplifier at its gate;
a charge pump that is coupled the switching node; and
a controller that is coupled to the sources of the NMOS and PMOS transistors and to the charge pump, wherein the controller provides a control signal to the charge pump based at least in part on a voltage at the switching node, and wherein the controller includes a comparator having a hysteresis that compares the voltage at the switching node to a second reference voltage.
2. The apparatus of claim 1 , wherein the power transistor is a PMOS transistor.
3. The apparatus of claim 1 , wherein the charge pump further comprises:
a first switch that is actuated and deactuated by the control signal;
a first current source that is coupled between the first switch and the switching node;
a second switch that is actuated and deactuated by the control signal, wherein the second switch is actuated when the first switch is deactuated, and wherein the second switch is deactuated when the first switch is actuated; and
a second current source that is coupled between the second switch and the switching node.
4. The apparatus of claim 1 , wherein the measuring circuit further comprises a voltage divider.
5. An apparatus for providing an output current and an output voltage to a load, the apparatus comprising:
a first voltage rail;
a second voltage rail;
a first PMOS transistor that is coupled to the first rail at its source and that is adapted to be coupled to the load at its drain;
a measuring circuit that is coupled to the power transistor, wherein the measuring circuit generates a feedback voltage;
an error amplifier that is coupled to the measuring circuit, wherein the error amplifier compares the feedback voltage to a first reference voltage;
an NMOS transistor that is coupled to the error amplifier at its gate, that is coupled to the first voltage rail at its drain, and that is coupled to the control electrode at its source on a switching node;
a PMOS transistor that is coupled to the switching node at its source, that is coupled to the second voltage rail at its drain, and that is coupled to the error amplifier at its gate;
a first switch that is coupled to the first voltage rail;
a first current source that is coupled between the first switch and the switching node;
a second switch that is coupled to the second voltage rail;
a second current source that is coupled between the second switch and the switching node; and
a comparator having a hysteresis, wherein the comparator is coupled to switching node, wherein the comparator compares a voltage at the switching node to a second reference voltage to generate a control signal that is provided to the first and second switches, and wherein the control signal is provided such that the second switch is actuated when the first switch is deactuated and the second switch is deactuated when the first switch is actuated.
6. The apparatus of claim 1 , wherein the measuring circuit further comprises a voltage divider.