Low RC global clock distribution
A semiconductor die includes: a clock distribution network that distributes a clock signal within the die. The clock distribution network includes: a clock tree corresponding to one or more metal layers of the die, a plurality of clock spines corresponding to a metal layer of the die, a plurality of clock wings corresponding to a metal layer of the die, a plurality of clock grid drivers placed in one or more gaps of a floorplan corresponding to the semiconductor layer of the die, a clock grid placed in the one or more gaps of the floorplan, a plurality of buffers placed in a local gain buffer pair configuration wherein the local gain buffer pair connects the clock grid to a shorting bar, and a plurality of conductors that connect the shorting bar to a plurality of loads.
1. A computer implemented method of designing a semiconductor die with a flexible floorplan comprising:
arranging a plurality of bumps that connect the die to a mechanical package, the plurality of bumps corresponding to a bump layout of the die;
placing a plurality of blocks in a floorplan corresponding to a semiconductor layer of the die;
placing a clock tree corresponding to one or more metal layers of the die;
placing a plurality of clock spines corresponding to a metal layer of the die; and
placing a plurality of clock wings corresponding to a metal layer of the die;
wherein the clock wings connect one or more of the plurality of clock spines to the clock tree; and
wherein the clock tree is comprised of a plurality of wires arranged at a planar angle of 45 degrees.
2. A computer implemented method of designing a semiconductor die with a flexible floorplan comprising:
arranging a plurality of bumps that connect the die to a mechanical package, the plurality of bumps corresponding to a bump layout of the die;
placing a plurality of blocks in a floorplan corresponding to a semiconductor layer of the die;
placing a clock tree corresponding to one or more metal layers of the die;
placing a plurality of clock spines corresponding and placing a plurality of clock wings corresponding to a metal layer of the die;
wherein the clock wings connect one or more of the plurality of clock spines to the clock tree,
wherein the clock tree is comprised of a plurality of wires arranged at a planar angle of 45 degrees; and
wherein the clock tree provides for diagonal clock routes.
3. A computer implemented method of designing a semiconductor die with a flexible floorplan comprising:
arranging a plurality of bumps that connect the die to a mechanical package, the plurality of bumps corresponding to a bump layout of the die;
placing a plurality of blocks in a floorplan corresponding to a semiconductor layer of the die;
placing a clock tree corresponding to one or more metal layers of the die;
placing a plurality of clock spines corresponding to a metal layer of the die; and
placing a plurality of clock wings corresponding to a metal layer of the die;
wherein the clock wings connect one or more of the plurality of clock spines to the clock tree;
placing a plurality of clock grid drivers in one or more gaps of the floorplan;
placing a clock grid in the one or more gaps of the floorplan, wherein the clock grid drivers connect one or more of the clock spines to the clock grid;
placing a plurality of buffers in a local gain buffer pair configuration, wherein the local gain buffer pair connects the clock grid to a shorting bar; and
placing a plurality of conductors that connect the shorting bar to a plurality of loads.
4. The method of claim 3 , the method further comprising:
clipping an unused portion of each clock wing.
5. The method of claim 3 , wherein the clock tree is comprised of a plurality of wires arranged at a planar angle of 45 degrees.
6. The method of claim 5 , wherein the clock tree provides for diagonal clock routes.
7. The method of claim 3 , wherein the local gain buffer pair corresponds to a second buffer and a third buffer as part of a three-stage FO4 local gain configuration.
8. A semiconductor device comprising:
a mechanical package; and
a semiconductor die comprising:
a semiconductor layer,
a plurality of metal layers,
a clock distribution network that distributes a clock signal within the die, and
a plurality of bumps that connect the die to the mechanical package;
wherein the clock distribution network comprises a low RC global clock distribution, the low RC global clock distribution comprising:
a clock tree corresponding to one or more metal layers of the die,
a plurality of clock spines corresponding to a metal layer of the die,
a plurality of clock wings corresponding to a metal layer of the die, wherein the clock wings connect one or more of the clock spines to the clock tree,
a plurality of clock grid drivers placed in one or more gaps of a floorplan corresponding to the semiconductor layer of the die;
a clock grid placed in the one or more gaps of the floorplan, wherein the clock grid drivers connect one or more of the clock spines to the clock grid,
a plurality of buffers placed in a local gain buffer pair configuration, wherein the local gain buffer pair connects the clock grid to a shorting bar, and
a plurality of conductors that connect the shorting bar to a plurality of loads.
9. The semiconductor device of claim 8 , wherein the unused portion of the clock wings are clipped.
10. The semiconductor device of claim 8 , wherein the clock tree is comprised of a plurality of wires arranged at a planar angle of 45 degrees.
11. The semiconductor device of claim 10 , wherein the clock tree provides for diagonal clock routes.
12. The semiconductor device of claim 10 , wherein the local gain buffer pair corresponds to a second buffer and a third buffer as part of a three-staged FO4 local gain configuration.
13. A system comprising:
an input device;
an output device;
a mechanical chassis;
a printed circuit board; and
a semiconductor device comprising:
a mechanical package, and
a semiconductor die;
wherein the semiconductor die comprises:
a semiconductor layer,
a plurality of metal layers,
a clock distribution network that distributes a clock signal within the die, and
a plurality of bumps that connect the die to the mechanical package; and
wherein the clock distribution network comprises a low RC global clock distribution, the low RC global clock distribution comprising:
a clock tree corresponding to one or more metal layers of the die,
a plurality of clock spines corresponding to a metal layer of the die,
a plurality of clock wings corresponding to a metal layer of the die, wherein the clock wings connect one or more of the clock spines to the clock tree,
a plurality of clock grid drivers placed in one or more gaps of a floorplan corresponding to the semiconductor layer of the die;
a clock grid placed in one or more gaps of the floorplan, wherein the clock grid drivers connect one or more of the clock spines to the clock grid,
a plurality of buffers placed in a local gain buffer pair configuration, wherein the local gain buffer pair connects the clock grid to a shorting bar, and
a plurality of conductors that connect the shorting bar to a plurality of loads.
14. The system of claim 13 , wherein the unused portion of the clock wings are clipped.
15. The system of claim 13 , wherein the clock tree is comprised of a plurality of wires arranged at a planar angle of 45 degrees.
16. The system of claim 15 , wherein the clock tree provides for diagonal clock routes.
17. The system of claim 13 , wherein the local gain buffer pair corresponds to a second buffer and a third buffer as part of a three-stage FO4 local gain configuration.