Data processing device, image encoding/decoding device and data processing system
To reduce a processing load of an external CPU, when a large amount of data is initially set frequently to an image coding/decoding device. The image encoding/decoding device (data processing device) includes a first circuit and a second circuit for providing initial setting to a plurality of image processing modules (processor units), wherein the image encoding/decoding device does not receive information, which is initially set to the image processing modules, directly from the external CPU, and control information for the initial setting is set to the first circuit from the CPU. The second circuit reads in initial setting information and setting-target information of the initial setting information from outside using the control information set in the first circuit and transfers the initial setting information to the image processing module according to the read-in setting-target information.
1. A data processing device, comprising:
a plurality of processor units performing data processing in parallel according to an initially set program and data;
a first circuit, to which control information is set from outside for initial setting, and
a second circuit reading-in initial setting information and setting-target information of the initial setting information from outside using the control information set in the first circuit, and transferring the initial setting information to the processor unit according to the read-in setting-target information.
2. An image encoding/decoding device, comprising:
a plurality of image processing modules enabled to perform encoding and decoding processing of image data according to initially set contents;
a first circuit, to which control information is set from outside for initial setting; and
a second circuit reading-in initial setting information and setting-target information of the initial setting information from outside using the control information set in the first circuit, and transferring the initial setting information to the image processing module according to the read-in setting-target information.
3. The image encoding/decoding device according to claim 2 , wherein
the control information includes address information indicating storage locations of the initial setting information and the setting-target information.
4. The image encoding/decoding device according to claim 3 , wherein
the control information includes address information indicating heads of the storage locations of the initial setting information and the setting-target information, and the second circuit sequentially increments the address information indicating the heads and sequentially generates read-in targets of the initial setting information and the setting-target information.
5. The image encoding/decoding device according to claim 2 , wherein
the setting-target information is information indicating which image processing module and information indicating an address of a storage area within the image processing module.
6. The image encoding/decoding device according to claim 4 , wherein
the initial setting information and the setting-target information constitute a fixed-length packet for each set of the setting-target information, each packet including a flag, and a first state of the flag indicating that the flag is followed by the initial setting information and a second state of the flag indicating that the packet is an end packet.
7. The image encoding/decoding device according to claim 6 , wherein
the second circuit completes the read-in of the initial setting information and the setting-target information, and completes transfer processing of the initial setting information according to the read-in information, in response to the flag of the end packet.
8. The image encoding/decoding device according to claim 6 , wherein
the second circuit transfers code information to the first circuit according to the address information following the flag of the end packet, and the first circuit instructs the image processing modules to start the image encoding and decoding processing in response to the transferred code information.
9. The image encoding/decoding device according to claim 2 , further comprising:
a plurality of processor units performing a plurality of sets of arithmetic processing for the encoding processing in parallel as the image processing modules; and
a plurality of processor units performing a plurality of sets of arithmetic processing for the decoding processing in parallel as the image processing modules.
10. The image encoding/decoding device according to claim 9 , wherein
a RAM, which is utilized for storing an operation program of the processor unit and data, is provided to each data processor and the initial setting information is initially set to the RAM.
11. A data processing system, comprising:
an image encoding/decoding device according to claim 8 ;
a CPU setting control information to a first circuit of the image encoding/decoding device; and
a storage unit storing the initial setting information and the setting-target information to be read-in by a second circuit of the image encoding/decoding device.
12. The data processing system according to claim 11 , wherein
the CPU sets the control information, which is necessary for selecting one from among a plurality of different encoding/decoding processing algorithms, to the first circuit of the image encoding/decoding device.
13. The data processing system according to claim 12 , being mounted on a mobile phone.