Semiconductor device
View Patent ↗A semiconductor device and manufacturing method satisfies both of the trade-off characteristic advantages of the HBT and the HFET. The semiconductor device is an HBT and HFET integrated circuit. The HBT includes a sub-collector layer, a GaAs collector layer, a GaAs base layer, and an InGaP emitter layer that are sequentially stacked. The sub-collector layer includes a GaAs external sub-collector region, and a GaAs internal sub-collector region disposed on the GaAs external sub-collector region. A mesa-shaped collector part and a collector electrode are separately formed on the GaAs external sub-collector region. The HFET includes a GaAs cap layer, a source electrode, and a drain electrode. The GaAs cap layer includes a portion of the GaAs external sub-collector region. The source electrode and the drain electrode are formed on the GaAs cap layer.
1. A semiconductor device, comprising:
a heterojunction bipolar transistor and a heterojunction field effect transistor formed on a same semiconductor substrate,
wherein the heterojunction bipolar transistor includes a sub-collector layer, a collector layer, a base layer, and an emitter layer which are sequentially stacked,
said sub-collector layer includes an external sub-collector region, and an internal sub-collector region disposed on said external sub-collector region,
a mesa-shaped collector part and a collector electrode are separately formed on said external sub-collector region, said collector part including said base layer, said emitter layer, said collector layer, and said internal sub-collector region,
the heterojunction field effect transistor includes a cap layer, a source electrode, and a drain electrode, said cap layer including a portion of said external sub-collector region, and said source electrode and said drain electrode being formed on said cap layer,
said cap layer is stacked commonly with said external sub-collector region, and has a same thickness as a thickness of said external sub-collector region,
said external sub-collector region has a thickness between not less than 50 nm and not more than 300 nm, and
said internal sub-collector region has a thickness of not less than 300 nm.
2. The semiconductor device according to claim 1 ,
wherein said collector electrode is separated from said collector part by not more than 1.5 μm in distance.
3. The semiconductor device according to claim 2 ,
wherein said sub-collector layer further includes an etching stopper region, which is inserted between said internal sub-collector region and said external sub-collector region, and which is made of a different material from a material of said external sub-collector region and said internal sub-collector region.
4. The semiconductor device according to claim 1 ,
wherein said sub-collector layer further includes an etching stopper region, which is inserted between said internal sub-collector region and said external sub-collector region, and which is made of a different material from a material of said external sub-collector region and said internal sub-collector region.