Method and system for providing a power-on reset pulse
View Patent ↗Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal.
1. A reset circuit, comprising;
a level detector;
a delay circuit, the delay circuit and the level detector being configured to receive a same input voltage signal; and
a counter having(i) a first input port coupled, at least indirectly, to an output port of the level detector and an output port of the delay circuit and (ii) an output port coupled, at least indirectly, to respective first input ports of the level detector and the delay circuit.
2. The reset circuit of claim 1 , further comprising a clock having an output port coupled to a second counter input port.
3. The reset circuit of claim 2 , further comprising a first logic gate having input ports respectively coupled to the level detector output port and the delay circuit output port, a first logic gate output port being coupled, at least indirectly, to the first counter input port.
4. The reset circuit of claim 3 , further comprising a second logic gate having (i) an input port coupled to the counter output port and (ii) an output port coupled to a second input port of the level detector.
5. The reset circuit of claim 4 , further comprising a third logic gate having (i) an input port coupled to the first logic gate output port and (ii) an output port coupled to the counter first input port; and
a fourth logic gate (i) having an input port coupled to the second logic gate output port and (ii) configured to provide a reset signal as an output therefrom.
6. The reset circuit of claim 5 , wherein the level detector and the delay circuit are formed on a single integrated circuit (IC).
7. The reset circuit of claim 6 , wherein the first logic gate is a NAND gate.