HIGH BANDWIDTH, EFFICIENT GRAPHICS HARDWARE ARCHITECTURE
The present invention relates to a system according to claim 1 , where the pixel buffer cache comprises at least one row descriptor for tracking and monitoring the activities of read and write requests of a particular tile. A system for providing a high bandwidth memory access to a graphics processor comprising: (a) a frame buffer for storing at least one frame, where said frame is stored in a tiled manner; (b) a memory controller for controlling said frame buffer; (c) a pixel buffer cache for storing multiple sections of at least one memory row of said frame buffer, and for processing requests to access pixels of said frame buffer; (d) a graphics accelerator having an interface to said pixel buffer cache for processing a group of related pixels; and (e) a CPU for processing graphic commands and controlling said graphics accelerator and said pixel buffer cache.
1 . A system for providing a high bandwidth memory access to a graphics processor comprising:
a. a frame buffer for storing at least one frame, where said frame is stored in a tiled manner;
b. a memory controller for controlling said frame buffer;
c. a pixel buffer cache for storing multiple sections of at least one memory row of said frame buffer, and for processing requests to access pixels of said frame buffer;
d. a graphics accelerator having an interface to said pixel buffer cache for processing a group of related pixels; and
e. a CPU for processing graphic commands and controlling said graphics accelerator and said pixel buffer cache.
2 . A system according to claim 1 , where the pixel buffer cache comprises at least one row descriptor for tracking and monitoring the activities of read and write requests of a particular tile.
3 . A system according to claim 1 , where the pixel buffer cache comprises an internal memory which can store at least one tile.
4 . A system according to claim 3 , where the pixel buffer cache comprises at least one read daemon which reads pixels from the frame buffer and writes them into the internal memory.
5 . A system according to claim 3 , where the pixel buffer cache comprises at least one sync daemon which finds the modified pixels in the internal memory and writes them into the frame buffer.
6 . A system according to claim 1 , where the graphics accelerator contains one or more line buffers for storing pixels.
7 . A system according to claim 6 , where each line buffer contains pixel memories and a control memory.
8 . A system according to claim 6 , where the graphics accelerator contains at least one DMA machine which transfers data between the line buffers and the pixel buffer cache.
9 . A system according to claim 1 , where the graphics accelerator contains a programmable micro-control unit.
10 . A system according to claim 9 , where the programmable micro-control unit performs vector graphics operations.
11 . A system according to claim 1 , where the graphics accelerator contains dedicated hardware for line drawing.
12 . A method for optimizing memory bandwidth to a graphics processor comprising the steps of:
a. receiving a request for rendering a geometric object;
b. dividing said request for geometric object into multiple burst requests;
c. transferring said burst requests to the pixel buffer cache;
d. calculating the address of the row of said pixel;
e. checking if said row is present in the pixel buffer cache;
activating row reclaim process if said row is not present in said pixel buffer cache; and
g. activating at least one daemon for transferring data between the internal memories of said pixel buffer cache and the frame buffer.