Thin film transistor array panel
View Patent ↗A thin film transistor array panel, in which a middle storage electrode and a storage electrode overlapping a drain electrode of a thin film transistor thereby forming a storage capacitance are formed. Accordingly, sufficient storage capacitance may be formed without a decrease of the aperture ratio and fight transmittance of a liquid crystal display. Also, the capacitance may be sufficiently formed through the connecting member connected to a gate metal layer.
1. A thin film transistor array panel comprising:
a substrate;
a gate line disposed on the substrate, the gate line including a gate electrode;
a storage electrode line disposed on the substrate, the storage electrode line including a storage electrode;
a gate insulating layer disposed on the gate line and the storage electrode line;
a semiconductor layer disposed on the gate insulating layer;
a data line disposed on the semiconductor layer and the gate insulating layer, the data line including a source electrode;
a drain electrode facing the source electrode on the semiconductor layer;
a lower layer disposed on the drain electrode;
a middle storage electrode disposed on the lower layer, the middle storage electrode overlapping the drain electrode and thereby forming a first storage capacitance;
an upper layer disposed on the middle storage electrode; and
a pixel electrode disposed on the upper layer, the pixel electrode being connected to the drain electrode.
2. The thin film transistor array panel of claim 1 , wherein the middle storage electrode overlaps the pixel electrode, thereby forming a second storage capacitance.
3. The thin film transistor array panel of claim 2 , wherein the storage electrode overlaps the drain electrode, thereby forming a third storage capacitance.
4. The thin film transistor array panel of claim 3 , wherein
the first storage capacitance is in the range of about 1.5-2.5 times the third storage capacitance.
5. The thin film transistor array panel of claim 4 , wherein
the second storage capacitance is in the range of about 0.1-0.3 times the first storage capacitance.
6. The thin film transistor array panel of claim 1 , wherein an area of the middle storage electrode is smaller than an area of the drain electrode.
7. The thin film transistor array panel of claim 1 , wherein the upper layer comprises an organic material.
8. The thin film transistor array panel of claim 7 , wherein the upper layer is thicker than the lower layer.
9. The thin film transistor array panel of claim 1 , further comprising a color filter disposed between the upper layer and the lower layer.
10. The thin film transistor array panel of claim 9 , wherein the middle storage electrode overlaps the pixel electrode, thereby forming the second storage capacitance.
11. The thin film transistor array panel of claim 1 , further comprising a light blocking member disposed on the lower layer.
12. The thin film transistor array panel of claim 1 , further comprising a middle storage electrode line disposed on the upper layer, the middle storage electrode line being connected to the middle storage electrode.
13. The thin film transistor array panel of claim 12 , further comprising a storage voltage supplying line disposed with the same layer as the data line,
wherein the storage voltage supplying line is connected to the middle storage electrode line.
14. The thin film transistor array panel of claim 13 , wherein the storage voltage supplying line is connected to the storage electrode line.