Scalable interface for connecting multiple computer systems which performs parallel MPI header matching

1. A compute node interface device for interfacing between a compute node and a fabric, wherein the compute node interface device comprises:

a memory, wherein the memory comprises a plurality of posted receive queues, wherein each of the posted receive queues is configured to store receive requests from a process executing on the compute node, wherein the receive requests include headers; and

a plurality of matcher units coupled to the memory, wherein each of the plurality of matcher units is implemented in hardware;

wherein for a first send request received by the compute node interface device, each of at least a first plural subset of the plurality of matcher units is configured to perform header matching in parallel to determine if a header in the first send request matches any headers in any of the plurality of posted receive queues;

wherein for a second send request received by the compute node interface device, each of at least a second plural subset of the plurality of matcher units is configured to perform header matching in parallel to determine if a header in the second send request matches any headers in any of the plurality of posted receive queues;

wherein the first plural subset of the plurality of matcher units and the second plural subset of the plurality of matcher units are configured to perform header matching for the first send request and the second send request concurrently;

wherein if a header in the send request matches a header of a receive request in one of the plurality of posted receive queues, the compute node interface device is configured to store the send request in a receive buffer.

2. The compute node interface device of claim 1 ,

wherein the plurality of matcher units is configured to perform header matching according to a Message Passing Interface (MPI) protocol.

3. The compute node interface device of claim 1 ,

wherein the first receive request comprises a header having a first field containing a wildcard value;

the compute node interface device further comprising:

a second memory coupled to the plurality of matcher units, wherein the second memory stores a header mask;

wherein at least one of the matcher units is operable to use the header mask during header matching to mask out the first field containing the wildcard value.

4. The compute node interface device of claim 1 ,

wherein the compute node comprises a host CPU and a host memory; and

wherein the plural subset of the plurality of matcher units perform header matching to implement a rendezvous data transfer protocol.

5. The compute node interface device of claim 1 ,

wherein the compute node interface device is configured to perform header matching for intra compute node transfers in response to a command received by host software executing on the compute node.

6. The compute node interface device of claim 1 ,

wherein the compute node interface device is configured to synchronize header matching with one or more other compute node interface devices that interface to the compute node.

7. The compute node interface device of claim 1 ,

wherein the compute node interface device is configured to dynamically adjust memory allocation of the posted receive queues for different processes executing on the compute node.

8. The compute node interface device of claim 1 ,

wherein the memory further comprises a plurality of unexpected queues; and

wherein if a header in the first send request does not match any headers in the plurality of posted receive queues, the compute node interface device is configured to store the header of the send request in one of the unexpected queues.

9. The compute node interface device of claim 8 ,

wherein when a new receive request is stored in one of the posted receive queues, at least a plural subset of the plurality of matcher units is configured to perform header matching to determine if a header in the new receive request matches any headers in any of the plurality of unexpected queues.

10. The compute node interface device of claim 8 ,

wherein the memory is dynamically partitioned among the plurality of posted receive queues and unexpected queues to provide separate queues for different applications or MPI ranks.

11. The compute node interface device of claim 8 ,

wherein the compute node comprises a host CPU and a host memory; and

wherein the compute node interface device is configured to implement at least a subset of the unexpected queues in the host memory of the compute node.

12. The compute node interface device of claim 8 , wherein the send request includes a payload comprising data;

the compute node interface device further comprising:

an unexpected message buffer coupled to the memory, wherein the unexpected message buffer is configured to store a payload of a send request that does not have a matching header in any of the plurality of posted receive queues.

13. The compute node interface device of claim 8 ,

wherein the compute node interface device is configured to dynamically adjust relative memory allocation of the posted receive queues and the unexpected queues.

14. A method for performing header matching in a first compute node, wherein the first compute node is in a cluster, the method comprising:

storing headers of receive requests from the first compute node in at least one posted receive queue;

receiving a first send request, wherein the first send request has a first send request header;

performing first header matching of the first send request header with headers of the receive requests stored in the at least one posted receive queue, wherein said first header matching is performed by a first plurality of hardware matching units concurrently accessing the at least one posted receive queue, wherein each of the first plurality of hardware units is implemented in hardware, wherein said header matching determines if the first send request header matches any headers of the receive requests in the at least one posted receive queue; and

if the first send request header matches a header in the at least one posted receive queue, storing the first send request in a receive buffer;

receiving a second send request, wherein the second send request has a second send request header;

performing second header matching of the first send request header with headers of the receive requests stored in the at least one posted receive queue, wherein said second header matching is performed by a second plurality of hardware matching units concurrently accessing the at least one posted receive queue, wherein each of the second plurality of hardware units is implemented in hardware, wherein said header matching determines if the second send request header matches any headers of the receive requests in the at least one posted receive queue;

wherein said performing first header matching and said performing second header matching are performed concurrently; and

if the second send request header matches a header in the at least one posted receive queue, storing the second send request in a receive buffer.

15. The method of claim 14 , further comprising:

if the first send request header does not match any headers in the at least one posted receive queue, storing the first send request header in at least one unexpected queue;

receiving another receive request after said storing the first send request header in the at least one unexpected queue;

performing header matching of a header of the another receive request and one or more send request headers in the unexpected queue, wherein said header matching is performed by a plurality of hardware matching units concurrently accessing the at least one unexpected queue; and

if the header of the another receive request matches the first send request header in the at least one unexpected queue, storing the first send request in a receive buffer indicated by the another receive request.

16. A compute node interface device for interfacing between a compute node and a fabric, wherein the compute node interface device comprises:

a memory, wherein the memory comprises a plurality of posted receive queues, wherein each of the posted receive queues is configured to store receive requests from a process executing on the compute node, wherein the receive requests include headers; and

a plurality of matcher units coupled to the memory, wherein each of the plurality of matcher units is implemented in hardware;

wherein a first plural subset of the plurality of matcher units is configured to perform header matching for a first send request;

wherein a second plural subset of the plurality of matcher units is configured to perform header matching for a second send request; and

wherein the first plural subset and the second plural subset are configured to operate concurrently;

wherein if a header in the send request matches a header of a receive request in one of the plurality of posted receive queues, the compute node interface device is configured to store the send request in a receive buffer.