IP Library Granted Patent US 8,413,010
Granted Patent B1
US 8,413,010 · App. 12/403,257 · Granted Apr 2, 2013

Data storage device employing high quality metrics when decoding logical block address appended to a data sector

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Quick Facts
Patent No.
US 8,413,010
App. No.
12/403,257
Granted
Apr 2, 2013
Kind
B1
Abstract

A data storage device is disclosed that receives a read command from a host, wherein the read command comprises a read logical block address (LBA_R). A target data sector is read in response to the LBA_R to generate a read signal. The read signal is processed to detect user data and redundancy data using a soft-output detector that outputs quality metrics for the user data and redundancy data. A high quality metric is assigned to the LBA_R, and errors are corrected in the user data using an error correction code (ECC) decoder in response to the quality metrics output by the soft-output detector and the quality metrics assigned to the LBA_R.

Claims (48)

1. A data storage device comprising control circuitry operable to:

receive a read command from a host, the read command comprising a read logical block address (LBA_R);

read a target data sector in response to the LBA_R to generate a read signal;

process the read signal to detect user data and redundancy data using a soft-output detector that outputs quality metrics QM for the user data and redundancy data;

assign a high quality metric LBA_QM to the LBA_R; and

first correct errors in the user data using an error correction code (ECC) decoder in response to the quality metrics QM output by the soft-output detector and the quality metric LBA_QM assigned to the LBA_R.

2. The data storage device as recited in claim 1 , further comprising:

a disk comprising a plurality of data tracks, wherein each data track comprises a plurality of data sectors; and

a head actuated over the disk.

3. The data storage device as recited in claim 1 , wherein the soft-output detector comprises a Viterbi detector.

4. The data storage device as recited in claim 1 , wherein the soft-output detector comprises a soft-input-output detector.

5. The data storage device as recited in claim 1 , wherein the ECC decoder comprises an iterative ECC decoder.

6. The data storage device as recited in claim 5 , wherein the iterative ECC decoder comprises a Low-Density Parity-Check (LDPC) decoder.

7. The data storage device as recited in claim 1 , wherein the control circuitry is further operable to:

receive a write command from the host, the write command comprising user data and a write logical block address (LBA_W);

generate redundancy data over the user data and the LBA_W; and

write the user data and the redundancy data to the target data sector.

8. The data storage device as recited in claim 7 , wherein the LBA_W is not written to the target data sector.

9. The data storage device as recited in claim 1 , wherein when the ECC decoder is unable to first correct the errors in the user data, the control circuitry is further operable to:

assign a low quality metric LBA_QM to the LBA_R; and

second correct errors in the user data and the LBA_R using the ECC decoder in response to the quality metrics QM output by the soft-output detector and the quality metric LBA_QM assigned to the LBA_R.

10. The data storage device as recited in claim 9 , wherein the control circuitry is further operable to send an error message to the host when the LBA_R is corrected.

11. The data storage device as recited in claim 10 , wherein the control circuitry is further operable to detect that the LBA_R was corrected by comparing the LBA_R received from the host to the LBA_R after the second correcting.

12. The data storage device as recited in claim 1 , further comprising a non-volatile semiconductor memory comprising a plurality of data blocks, wherein each data block comprises a plurality of data sectors.

13. A method of operating data storage device comprising:

receiving a read command from a host, the read command comprising a read logical block address (LBA_R);

reading a target data sector in response to the LBA_R to generate a read signal;

processing the read signal to detect user data and redundancy data using a soft-output detector that outputs quality metrics QM for the user data and redundancy data;

assigning a high quality metric LBA_QM to the LBA_R; and

first correcting errors in the user data using an error correction code (ECC) decoder in response to the quality metrics QM output by the soft-output detector and the quality metric LBA_QM assigned to the LBA_R.

14. The method as recited in claim 13 , wherein the data storage device comprises:

a disk comprising a plurality of data tracks, wherein each data track comprises a plurality of data sectors; and

a head actuated over the disk.

15. The method as recited in claim 13 , wherein the soft-output detector comprises a Viterbi detector.

16. The method as recited in claim 13 , wherein the soft-output detector comprises a soft-input-output detector.

17. The method as recited in claim 13 , wherein the ECC decoder comprises an iterative ECC decoder.

18. The method as recited in claim 17 , wherein the iterative ECC decoder comprises a Low-Density Parity-Check (LDPC) decoder.

19. The method as recited in claim 13 , further comprising:

receiving a write command from the host, the write command comprising user data and a write logical block address (LBA_W);

generating redundancy data over the user data and the LBA_W; and

writing the user data and the redundancy data to the target data sector.

20. The method as recited in claim 19 , wherein the LBA_W is not written to the target data sector.

21. The method as recited in claim 13 , wherein when the ECC decoder is unable to first correct the errors in the user data, further comprising:

assigning a low quality metric LBA_QM to the LBA_R; and

second correcting errors in the user data and the LBA_R using the ECC decoder in response to the quality metrics QM output by the soft-output detector and the quality metric LBA_QM assigned to the LBA_R.

22. The method as recited in claim 21 , further comprising sending an error message to the host when the LBA_R is corrected.

23. The method as recited in claim 22 , further comprising detecting that the LBA_R was corrected by comparing the LBA_R received from the host to the LBA_R after the second correcting.

24. The method as recited in claim 13 , wherein the data storage device comprises a non-volatile semiconductor memory comprising a plurality of data blocks, wherein each data block comprises a plurality of data sectors.

Assignments (8)
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2009
From: VASQUEZ, STEVEN R.; LEE, PATRICK J.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 022660/0774 →