Redistribution layer power grid
View Patent ↗An integrated circuit package including a first metal layer coupled to a bonding pad, a first redistribution layer coupled to the bonding pad, and a RDL to Metal (RTM) via coupled to a first surface of the metal layer and further coupled to a first surface of the first RDL is described. The IC package may further include additional metal layers and redistribution layers.
1. An integrated circuit (IC) package, comprising:
a first metal layer coupled to a bonding pad;
a first redistribution layer (RDL) coupled to the bonding pad; and
a RDL to Metal (RTM) via coupled to a first surface of the metal layer and further coupled to a first surface of the first RDL.
2. The package of claim 1 , further comprising:
a second metal layer coupled to the first metal layer;
an active layer, comprising a semiconductor device, coupled to the second metal layer.
3. The package of claim 2 , further comprising a metal layer via coupling the second metal layer to a second surface of the first metal layer.
4. The package of claim 1 , further comprising:
a second RDL coupled to the first RDL.
5. The package of claim 4 , further comprising an RDL via coupling a first surface of the second RDL layer to a second surface of the first RDL.
6. The package of claim 1 , further comprising a plurality of RTM vias coupling the first surface of the first RDL to the first surface of the first metal layer.
7. The package of claim 1 , wherein the first RDL comprises:
a plurality of RDL routes; and
an RDL power grid.
8. The package of claim 7 , wherein the RTM via is coupled to the first surface of the first RDL at the RDL power grid.
9. The package of claim 1 , wherein the first RDL distributes power to the first metal layer through the RTM.
10. The package of claim 4 , further comprising one or more additional RDLs coupled to the second RDL.
11. The package of claim 10 , further comprising an RDL via coupling a first surface of the second RDL layer to a second surface of the first RDL and coupling a second surface of the second RDL layer to a first surface of one of the one or more additional RDLs.
12. The package of claim 1 , wherein the bonding pad consists of a conductive material.
13. The package of claim 1 , wherein the RTM via consists of a conductive material.
14. The package of claim 1 , wherein the respective RTM via and the respective bonding pad, each provide a current path from the first RDL to the first metal layer.
15. The package of claim 5 , wherein the RDL via, the first RDL and the second RDL, in combination couple the bonding pad with solder bumps.
16. The package of claim 5 , wherein the solder bumps serve as a chip interface.