Thin film transistor substrate having thin film transistors with improved etching characteristics, method of manufacturing the same, and display apparatus having the same
View Patent ↗In a thin film transistor substrate, an active pattern of a thin film transistor includes a lower semiconductor pattern and an upper semiconductor pattern that are patterned through different process steps. The lower semiconductor pattern defines a channel area of the thin film transistor, and the upper semiconductor pattern is connected to a side portion of the lower semiconductor pattern and makes contact with the source electrode and the drain electrode. An etch stop layer is formed on the lower semiconductor pattern corresponding to the channel area, and the etch stop layer is formed through the same patterning process as the lower semiconductor pattern. Also, an ohmic contact pattern is formed on the upper semiconductor pattern, and the ohmic contact pattern is formed by the same patterning process as the upper semiconductor pattern.
1. A thin film transistor substrate comprising:
a substrate;
a lower semiconductor pattern arranged on the substrate;
an etch stop layer arranged on the lower semiconductor pattern;
an upper semiconductor pattern arranged on the etch stop layer;
a source electrode arranged on the upper semiconductor pattern;
a drain electrode arranged on the upper semiconductor pattern and spaced apart from the source electrode; and
a gate electrode arranged on or under the lower semiconductor pattern to overlap the lower semiconductor pattern;
wherein the lower semiconductor pattern has a same shape as the etch stop layer in a plan view, and
wherein the upper semiconductor pattern contacts a side portion of the lower semiconductor pattern.
2. The thin film transistor substrate of claim 1 , further comprising an ohmic contact pattern arranged on the upper semiconductor pattern.
3. The thin film transistor substrate of claim 2 , wherein the ohmic contact pattern has a same shape as the upper semiconductor pattern in a plan view.
4. The thin film transistor substrate of claim 1 , wherein the upper semiconductor pattern and the lower semi-conductor pattern comprise crystalline silicon.
5. The thin film transistor substrate of claim 1 , wherein the upper semiconductor pattern comprises an impurity-doped semiconductor material.
6. A display apparatus comprising:
a first substrate;
a second substrate facing the first substrate;
a thin film transistor arranged on the first substrate; and
a pixel arranged on the first substrate and electrically connected to the thin film transistor;
wherein the thin film transistor comprises:
a lower semiconductor pattern arranged on the first substrate;
an etch stop layer arranged on the lower semiconductor pattern;
an upper semiconductor pattern arranged on the etch stop layer;
a source electrode arranged on the upper semiconductor pattern;
a drain electrode arranged on the upper semiconductor pattern and spaced apart from the source electrode; and
a gate electrode arranged on or under the lower semiconductor pattern to overlap the lower semiconductor pattern; and
wherein the lower semiconductor pattern has a same shape as the etch stop layer in a plan view,
wherein the upper semiconductor pattern contacts a side portion of the lower semiconductor pattern.
7. The display apparatus of claim 6 , wherein the thin film transistor further comprises an ohmic contact pattern arranged on the upper semiconductor pattern.
8. The display apparatus of claim 7 , wherein the ohmic contact pattern has a same shape as the upper semiconductor pattern in a plan view.
9. The display apparatus of claim 6 , wherein the upper semiconductor pattern and the lower semiconductor pattern comprise crystalline silicon.
10. The display apparatus of claim 6 , wherein the pixel comprises an organic light emitting layer that is electrically connected to the drain electrode.
11. The display apparatus of claim 6 , further comprising a liquid crystal disposed between the first substrate and the second substrate, and wherein the pixel comprises a pixel electrode that is electrically connected to the drain electrode.