Analog-to-digital converter with a balanced output

1. An analog-to-digital converter (ADC) comprising:

analog to digital conversion circuitry configured to receive an analog signal and output a digital representation of said analog signal on a plurality of data lines; and

a balancing circuit configured to encode said digital representation of said analog signal on said data lines such that a total number of 1's transmitted on any said data line is equal to a total number of 0's transmitted on said data line, said balancing circuit being further configured to periodically insert a synchronizing character into said output; and, serialization circuitry configured to serialize a parallel output from said analog-to-digital conversion circuitry at a rate faster than is required for transmitting data encoded by said balancing circuit such that insertion of said synchronizing character does not affect a throughput of said encoded data.

2. The ADC of claim 1 , wherein said analog to digital conversion circuitry is configured to produce said output in a data-stream immediately following said synchronizing character such that said synchronizing character also frames said output from said analog to digital conversion circuitry.

3. The ADC of claim 1 , wherein said analog to digital conversion circuitry is configured to sample said analog signal according to a sampling clock; and said balancing circuit is configured to encode said digital representation using a clock that is an integer multiple of said sampling clock.

4. The ADC of claim 1 , wherein said balancing circuit comprises an 8bit/10 bit (8B/10B) encoder.

5. The ADC of claim 4 , wherein said encoder does not generate odd fractional harmonics.

6. A method of performing Analog-to-Digital Conversion comprising balancing an output of analog to digital conversion circuitry such that a total number of 1's and 0's transmitted on any of a number of output data lines is the same periodically inserting a synchronizing character into said output; and, serializing said output at a rate faster than is required for sending encoded data such that insertion of said synchronizing character does not affect throughput of said encoded data.

7. The method of claim 6 , wherein said synchronizing character frames data content in said output.

8. The method of claim 6 , further comprising clocking said output with a clock that is an integer multiple of a sampling clock used by said analog to digital conversion circuitry to sample an analog signal being converted to a digital signal.

9. The method of claim 6 , wherein said balancing said output of said analog to digital conversion circuitry comprises encoding said output using 8B/10B encoding.

10. The method of claim 9 , further comprising outputting a separate signal to indicate an 8B/10B character boundary.