IP Library Granted Patent US 7,939,386
Granted Patent B2
US 7,939,386 · App. 12/409,453 · Granted May 10, 2011

Image sensor applied with device isolation technique for reducing dark signals and fabrication method thereof

Assignee: Crosstek Capital, LLC
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Quick Facts
Patent No.
US 7,939,386
App. No.
12/409,453
Granted
May 10, 2011
Kind
B2
Abstract

The present invention relates to an image sensor applied with a device isolation technique for reducing dark signals and a fabrication method thereof. The image sensor includes: a logic unit; and a light collection unit in which a plurality of photodiodes is formed, wherein the photodiodes are isolated from each other by a field ion-implantation region formed under a surface of a substrate and an insulation layer formed on the surface of the substrate.

Claims (67)

1. A method for fabricating an image sensor, the method comprising:

forming an insulation layer pattern on a substrate in a light collection unit region of the image sensor;

forming an insulation layer configured to provide device isolation in a logic unit region of the image sensor; and

forming a field ion-implantation region under a surface of the substrate in the light collection unit region.

2. A method for fabricating an image sensor, the method comprising:

forming an oxide layer on both a logic unit portion and a pixel array unit portion of the image sensor such that the oxide layer formed on the logic unit portion has a first thickness and the oxide layer formed on the pixel array unit portion has a different second thickness;

forming an ion-implantation region under the oxide layer in the pixel array unit portion; and

forming an insulation layer in the logic unit portion.

3. The method of claim 1 , wherein said forming an insulation layer pattern comprises forming the insulation layer pattern with inclined sidewalls.

4. The method of claim 1 , wherein said forming an insulation layer pattern comprises:

stacking an oxide layer and a nitride layer on the substrate;

forming a mask pattern on the nitride layer, wherein the mask pattern opens an active region of the light collection unit region;

applying a dry etching process to the nitride layer and the oxide layer while using the mask pattern as an etch mask;

after said applying a dry etching process to the nitride layer and the oxide layer, applying a wet etching process to the nitride layer and the oxide layer while using the mask pattern as an etch mask; and

removing the mask pattern and the nitride layer.

5. The method of claim 4 , wherein said applying a dry etching process to the nitride layer and the oxide layer forms an undercut at a bottom portion of each sidewall of the nitride layer.

6. The method of claim 4 , wherein said applying a dry etching process to the nitride layer and the oxide layer results in the oxide layer having a thickness ranging from about 600 Å to about 700 Å.

7. The method of claim 4 , further comprising using a thermal process to grow the oxide layer.

8. The method of claim 2 , wherein said forming an oxide layer comprises:

forming a nitride layer on the oxide layer;

forming an isolation mask pattern only on the nitride layer formed over the pixel array unit portion;

etching the oxide layer and the nitride layer using the isolation mask pattern; and

removing the isolation mask pattern and the nitride layer.

9. The method of claim 2 , wherein said forming an ion-implantation region comprises using a selective ion-implantation process to form the ion-implantation region.

10. The method of claim 2 , further comprising:

forming a plurality of photodiodes in the pixel array unit portion, wherein said forming an ion-implantation region comprises using a selective ion-implantation process to isolate the plurality of photodiodes from each other.

11. The method of claim 2 , further comprising:

forming the logic unit portion and the pixel array unit portion in a substrate having a first conductive type; and

forming a plurality of photodiodes having a second conductive type in the pixel array unit portion, wherein said forming an ion-implantation region comprises using a selective ion-implantation process to form the ion-implantation region having the first conductive type to isolate the plurality of photodiodes from each other.

12. The method of claim 2 , wherein said forming an insulation layer in the logic unit portion comprises:

forming a pad oxide layer in the logic unit portion;

forming a pad nitride layer on the pad oxide layer;

forming an isolation mask pattern on the pad nitride layer;

using the isolation mask pattern to form the insulation layer via a thermal process; and

removing the pad oxide layer and the pad nitride layer.

13. The method of claim 2 , wherein said forming an insulation layer in the logic unit portion comprises:

forming a pad oxide layer in the logic unit portion;

forming a pad nitride layer on the pad oxide layer;

forming an isolation mask pattern on the pad nitride layer;

using the isolation mask pattern to form the insulation layer via a local oxidation of silicon (LOCOS) technique; and

removing the pad oxide layer and the pad nitride layer.

14. The method of claim 2 , wherein said forming an insulation layer in the logic unit portion comprises:

forming a pad oxide layer in the logic unit portion;

forming a pad nitride layer on the pad oxide layer;

forming an isolation mask pattern on the pad nitride layer;

using the isolation mask pattern to form the insulation layer via a shallow trench isolation (STI) technique; and

removing the pad oxide layer and the pad nitride layer.

15. The method of claim 2 , wherein said forming an insulation layer in the logic unit portion comprises using a thermal process to grow an oxide layer of the insulation layer.

16. The method of claim 15 , wherein the oxide layer of the insulation layer is grown to a thickness that accounts for ion-implantation energy to be used by a subsequent ion-implantation process.

17. A method for fabricating an image sensor, the method comprising:

forming a plurality of devices in a logic unit portion of a substrate for the image sensor;

forming a plurality of photodiodes in a light collection portion of the substrate;

using a thermal oxidation process to isolate devices from the plurality of devices;

after said using a thermal oxidation process, using an ion-implantation process to isolate photodiodes from the plurality of photodiodes.

18. The method of claim 17 , wherein said using a thermal oxidation process comprises forming an insulation layer pattern having inclined sidewalls.

19. The method of claim 18 , wherein said forming an insulation layer pattern comprises:

stacking an oxide layer and a nitride layer on the substrate;

forming a mask pattern on the nitride layer, wherein the mask pattern opens an active region of the light collection portion;

applying a dry etching process to the nitride layer and the oxide layer while using the mask pattern as an etch mask;

after said applying a dry etching process to the nitride layer and the oxide layer, applying a wet etching process to the nitride layer and the oxide layer while using the mask pattern as an etch mask; and

removing the mask pattern and the nitride layer.

20. The method of claim 19 , wherein said applying a dry etching process to the nitride layer and the oxide layer forms an undercut at a bottom portion of each sidewall of the nitride layer.

21. The method of claim 19 , wherein said applying a dry etching process to the nitride layer and the oxide layer results in the oxide layer having a thickness ranging from about 600 Å to about 700 Å.

22. The method of claim 17 , wherein:

the substrate has a first conductive type;

the plurality of photodiodes have a second conductive type; and

an ion-implantation region formed by the ion-implantation process has the first conductive type and isolates the plurality of photodiodes from each other.

Assignments (3)
MERGER Recorded Jul 22, 2011
From: CROSSTEK CAPITAL, LLC
To: INTELLECTUAL VENTURES II LLC
Reel/Frame 026637/0632 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: CROSSTEK CAPITAL, LLC
Reel/Frame 022834/0077 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: CROSSTEK CAPITAL, LLC
Reel/Frame 022764/0270 →
Priority Claims (1)
KR 2003-91843 · Dec 16, 2003 · national
Continuity (3)
Continuation 11890991 · Aug 8, 2007
Division 10882846 · Jun 30, 2004
Related Publication 20090191662A1 · Jul 30, 2009