SOI radio frequency switch with enhanced electrical isolation
View Patent ↗At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.
1. A method of forming a semiconductor structure comprising:
forming at least two field effect transistors on a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate;
forming a shallow trench isolation structure in said top semiconductor layer, wherein said shallow trench isolation structure laterally abuts and surrounds said at least two field effect transistors;
forming a middle-of-line (MOL) dielectric layer over said at least two field effect transistors and said shallow trench isolation structure; and
forming at least one conductive via extending from a top surface of said MOL dielectric layer through said MOL dielectric layer, said shallow trench isolation structure, a buried insulator layer, and to a top surface of a bottom semiconductor layer of said SOI substrate, wherein said at least one conductive via is interposed between said at least two field effect transistors and separates said at least two field effect transistors, and said at least one conductive via laterally surrounds said at least two field effect transistors and does not contact any semiconductor material in said top semiconductor layer.
2. The method of claim 1 , further comprising:
forming at least one via cavity extending from said top surface of said MOL dielectric layer to said top surface of said bottom semiconductor layer; and
filling said at least one via cavity with a conductive material, wherein said at least one conductive via is formed by said conductive material that fills said at least one via cavity.
3. The method of claim 2 , wherein each of said at least one conductive via comprises a doped semiconductor material or a metallic material.
4. The method of claim 1 , wherein each of said at least one conductive via is of unitary construction and extends from said top surface of said MOL dielectric layer to said top surface of said bottom semiconductor layer.
5. The method of claim 1 , further comprising:
forming at least one via cavity extending from a top surface of said shallow trench isolation structure to said top surface of said bottom semiconductor layer; and
filling said at least one via cavity with a conductive material, wherein at least one lower conductive via is formed by said conductive material that fills said at least one via cavity.
6. The method of claim 1 , wherein said at least one conductive via is laterally spaced from any semiconductor material in said top semiconductor layer by said shallow trench isolation structure.
7. The method of claim 1 , further comprising forming a constant voltage source configured to electrically bias said bottom semiconductor layer of said SOI substrate and said at least one conductive via through a metal interconnect structure at a constant voltage that is different from a voltage of electrical ground.
8. A method of operating a semiconductor device comprising:
providing a semiconductor device including:
at least two field effect transistors located on a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate;
a shallow trench isolation structure laterally abutting said at least two field effect transistors; and
at least one conductive via extending from a top surface of a middle-of-line (MOL) dielectric layer through said MOL dielectric layer, said shallow trench isolation structure, a buried insulator layer, and to a top surface of a bottom semiconductor layer of said SOI substrate, wherein said at least one conductive via is interposed between said at least two field effect transistors and separates said at least two field effect transistors, and said at least one conductive via laterally surrounds said at least two field effect transistors and does not contact any semiconductor material in said top semiconductor layer;
applying a radio frequency (RF) signal to at least one of said at least two field effect transistors, wherein an induced charge layer is formed directly underneath said buried insulator layer; and
electrically biasing said bottom semiconductor layer of said SOI substrate and said at least one conductive via at a constant voltage.
9. The method of claim 8 , wherein said induced charge layer changes thickness in time at a signal frequency of said RF signal in said at least one of said at least two field effect transistors.
10. The method of claim 8 , wherein charges in said induced charge layer changes polarity in time at a signal frequency of said RF signal in said at least one of said at least two field effect transistors.
11. The method of claim 8 , wherein said constant voltage is a voltage that is equal to or less than a first voltage at a maximum positive swing of said RF signal and is equal to or greater than a second voltage at a maximum negative swing of said RF signal.
12. The method of claim 11 , wherein said bottom semiconductor layer and said at least one conductive via are electrically grounded.
13. The method of claim 8 , wherein said at least one conductive via is laterally spaced from any semiconductor material in said top semiconductor layer by said shallow trench isolation structure.
14. The method of claim 8 , wherein said constant voltage is different from a voltage of electrical ground.
15. A method of forming a semiconductor structure comprising:
forming a shallow trench isolation structure laterally surrounding at least one portion of a top semiconductor layer and contacting a top surface of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate;
forming a field effect transistor on each of said at least one portion;
forming a middle-of-line (MOL) dielectric layer over said at least one field effect transistor and said shallow trench isolation structure; and
forming at least one conductive via extending from a top surface of said MOL dielectric layer through said MOL dielectric layer, said shallow trench isolation structure, a buried insulator layer, and to a top surface of a bottom semiconductor layer of said SOI substrate, wherein said at least one conductive via is laterally spaced from any semiconductor material in said top semiconductor layer by said shallow trench isolation structure and said at least one conductive via laterally surrounds said at least one portion of said top semiconductor layer.
16. The method of claim 15 , wherein said shallow trench isolation structure laterally surrounds at least two portions of said top semiconductor layer.
17. The method of claim 16 , wherein said at least one field effect transistor includes at least two field effect transistors including a first field effect transistor formed on a first portion of said at least two portions of said top semiconductor layer and a second field effect transistor formed on a second portion of said at least two portions of said top semiconductor layer.
18. The method of claim 17 , wherein said at least one conductive via laterally surrounds said first portion and said second portion.
19. The method of claim 15 , wherein at least a portion of said at least one conductive via extends between a top surface of said top semiconductor layer and said top surface of said bottom semiconductor layer, and contiguously extends at least throughout an entirety of said portion of said at least one conductive via.
20. The method of claim 19 , wherein said at least one conductive via is a stack of two conductive vias including an upper conductive via and a lower conductive via that is said portion of said at least one conductive via, a physically manifested interface exists between said upper conductive via and said lower conductive via, and upper conductive via contiguously extends between said top surface of said top semiconductor layer and said top surface of said MOL dielectric layer.
21. The method of claim 15 , wherein said at least one conducive via is a single conductive via that contiguously extends between said top surface of said bottom semiconductor layer and said top surface of said MOL dielectric layer.
22. The method of claim 15 , further comprising:
forming at least one via cavity extending from said top surface of said MOL dielectric layer to said top surface of said bottom semiconductor layer; and
filling said at least one via cavity with a conductive material, wherein said at least one conductive via is formed by said conductive material that fills said at least one via cavity.
23. The method of claim 22 , wherein each of said at least one conductive via comprises a doped semiconductor material or a metallic material.
24. The method of claim 15 , further comprising:
forming at least one via cavity extending from a top surface of said shallow trench isolation structure to said top surface of said bottom semiconductor layer; and
filling said at least one via cavity with a conductive material, wherein a lower conductive via is formed by said conductive material that fills said at least one via cavity.
25. The method of claim 15 , further comprising forming a constant voltage source configured to electrically bias said bottom semiconductor layer of said SOI substrate and said at least one conductive via at a constant voltage that is different from a voltage of electrical ground.