IP Library Granted Patent US 8,368,678
Granted Patent B2
US 8,368,678 · App. 12/412,033 · Granted Feb 5, 2013

Pixel circuit, display apparatus, and pixel circuit drive control method

Inventor: Yasuhiro Seto (Ashigarakami-gun, JP)
Assignee: FUJIFILM Corporation
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Quick Facts
Patent No.
US 8,368,678
App. No.
12/412,033
Granted
Feb 5, 2013
Kind
B2
Abstract

A pixel circuit including a light emitting element, a driving transistor, connected to the light emitting element, that applies a drive current to the light emitting element, a holding circuit connected to a gate terminal of the driving transistor, and a switching transistor connected between the holding circuit and a data line through which a data signal to be held by the holding circuit flows, in which the driving transistor and the switching transistor are inorganic oxide thin film transistors whose OFF-operation threshold voltage is a negative voltage, and the holding circuit includes a first capacitor element connected between the switching transistor and the gate terminal of the driving transistor, and a second capacitor element connected between a point located between the first capacitor element and the gate terminal of the driving transistor and a voltage source that supplies a negative voltage.

Claims (21)

1. A pixel circuit comprising:

a light emitting element,

a driving transistor, connected to the light emitting element, that applies a drive current to the light emitting element,

a holding circuit connected to a gate terminal of the driving transistor, and

a switching transistor connected between the holding circuit and a data line through which a data signal to be held by the holding circuit flows, wherein:

the driving transistor and the switching transistor are inorganic oxide thin film transistors whose OFF-operation threshold voltage is a negative voltage; and

the holding circuit includes a first capacitor element connected between the switching transistor and the gate terminal of the driving transistor, and a second capacitor element connected between a point located between the first capacitor element and the gate terminal of the driving transistor and a voltage source that supplies a negative voltage.

2. A display apparatus, comprising

an active matrix substrate on which a pixel circuit is disposed in a large number, the pixel circuit comprising:

a light emitting element,

a driving transistor, connected to the light emitting element, that applies a drive current to the light emitting element,

a holding circuit connected to a gate terminal of the driving transistor, and

a switching transistor connected between the holding circuit and a data line through which a data signal to be held by the holding circuit flows, wherein:

the driving transistor and the switching transistor are inorganic oxide thin film transistors whose OFF-operation threshold voltage is a negative voltage; and

the holding circuit includes a first capacitor element connected between the switching transistor and the gate terminal of the driving transistor, and a second capacitor element connected between a point located between the first capacitor element and the gate terminal of the driving transistor and a voltage source that supplies a negative voltage;

a scan drive circuit that supplies to each switching transistor a scanning signal for turning ON/OFF each switching transistor; and

a data drive circuit that supplies the data signal to be held by the holding circuit,

wherein the scan drive circuit is a circuit that supplies a positive voltage as the scanning signal and the data drive circuit is a circuit that supplies a positive voltage as the data signal.

3. The display apparatus as claimed in claim 2 , the negative voltage VB supplied to the second capacitor element, a capacitance C 1 of the first capacitor element, a capacitance C 2 of the second capacitor element, and the threshold voltage VTH satisfy the relationship of Formula (1) below, and a minimum setting value V datamin of the data signal, an OFF scan signal V scan(off) , and the threshold voltage VTH satisfy the relationship of Formula (2) below,

VB ≦(1+2 ×C 2 /C 1)× VTH   (1)

V datamin ≧V scan(off) −VTH   (2).

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2022
From: FUJIFILM CORPORATION
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 061486/0083 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2009
From: SETO, YASUHIRO
To: FUJIFILM CORPORATION
Reel/Frame 022457/0130 →
Priority Claims (1)
JP 2008-079794 · Mar 26, 2008 · national
Continuity (1)
Related Publication 20090244046A1 · Oct 1, 2009