LOCK-FREE SCHEDULER WITH PRIORITY SUPPORT
Techniques for implementing a lock-free scheduler with ordering support are described herein. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present disclosure. It can be appreciated by one of skill in the art that one or more various aspects of the disclosure may include but are not limited to circuitry and/or programming for effecting the herein-referenced aspects of the present disclosure; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the herein-referenced aspects depending upon the design choices of the system designer.
1 . A computer readable storage medium including processor executable instructions, the computer readable storage medium comprising:
instructions for storing a thread in a linked list associated with a specific processor of a plurality of processors in a computer system, the linked list accessible to the plurality of processors;
instructions for adding the thread stored in the linked list to a ready list associated with the specific processor, the ready list is only accessible to the specific processor and the threads are stored in the ready list in an order of priority; and
instructions for executing the thread.
2 . The computer readable storage medium of claim 1 , further comprising:
instructions for determining that the linked list is empty;
instructions for adding the thread to the linked list; and
instructions for sending an interrupt to the specific processor.
3 . The computer readable storage medium of claim 1 , further comprising:
instructions for determining that the linked list is not empty; and
instructions for adding another thread to the linked list.
4 . The computer readable storage medium of claim 1 , wherein the instructions for adding the thread stored in the linked list to the ready list further comprises:
instructions for setting a head entry in the linked list to an active state, the active state indicating that the specific processor is accessing the linked list; and
instructions for inserting the thread into to the ready list in order of priority;
instructions for setting the head entry in the linked list to an empty state.
5 . The computer readable storage medium of claim 1 , further comprising:
instructions for storing an operating system thread in a linked list associated with a virtual machine, the linked list accessible to the plurality of processors;
instructions for adding the operating system thread stored in the linked list to a ready list associated with a specific processor, the ready list is only accessible to the specific processor and operating system threads are stored in the ready list in order of priority; and
instructions for executing the operating system thread.
6 . The computer readable storage medium of claim 1 , further comprising:
instructions for placing the specific processor into an idle state and configuring the specific processor to monitor the linked list;
instructions for detecting that the thread was written to the linked list; and
instructions for exiting the idle state.
7 . The computer readable storage medium of claim 1 , wherein the instructions for storing the thread in the linked list further comprise:
instructions for executing an atomic compare and swap operation on the linked list to add the thread to the linked list.
8 . A computer system, comprising:
circuitry for determining that a linked list for a processor is empty, the linked list configured to store threads;
circuitry for adding a thread to the linked list and sending an interrupt to the processor;
circuitry for determining that the thread was added to the linked list for the processor in response to receiving the interrupt; and
circuitry for adding the thread to a ready list for the processor, the processor configured to execute threads from the ready list in an order of thread priority, and the ready list is exclusively accessible by the processor.
9 . The computer system of claim 8 , further comprising:
circuitry for determining that the linked list for the processor is not empty; and
circuitry for adding an additional thread to the linked list.
10 . The system of claim 8 , wherein the thread is a virtual processor thread.
11 . The system of claim 8 , wherein the circuitry for adding the thread to the ready list further comprises:
circuitry for setting a head entry in the linked list to an active state, the active state indicating that the processor is accessing the linked list; and
circuitry for inserting the information related to the pending thread into the ready list in order of priority; and
circuitry for setting the head entry in the linked list to an empty state.
12 . The system of claim 8 , wherein the circuitry for adding the thread to the linked list further comprises:
circuitry for executing an atomic compare and swap operation on the linked list to add the thread to the linked list.
13 . The system of claim 11 , further comprising:
circuitry for determining that the head entry in the linked list was changed from the active state;
circuitry for identifying an additional thread that was added to the linked list; and
circuitry for inserting the thread into the ready list based on the additional thread's priority.
14 . A method, comprising:
entering, by a processor, an idle state, wherein the processor is configured to monitor a memory address associated with a linked list while in the idle state;
detecting, by the processor, that a thread was added to the linked list and exiting the idle state; and
adding the thread to a ready list for the processor, the processor configured to execute threads from the ready list in an order of priority and the ready list is exclusively accessible by the processor.
15 . The method of claim 14 , wherein adding the thread to the ready list further comprises:
setting a head entry in the linked list to an active state, the active state indicating that the specific processor is accessing the linked list;
inserting the thread into to the ready list in order of priority; and
setting the head entry in the linked list to an empty state.
16 . The method of claim 14 , further comprising:
writing, by the processor, information to a shared memory location, the information identifying that the processor is entering the idle state.
17 . The method of claim 14 , further comprising:
setting, by the processor, a head entry for the linked list to a value that indicates that the linked list is empty.
18 . The method of claim 15 , wherein setting the head entry in the linked list to the empty state further comprises:
executing an atomic compare and swap operation on the linked list to set the head entry to the empty state.
19 . The method of claim 16 , further comprising:
determining, by a second processor, that the first processor has entered the idle state from the information in the shared memory location; and
adding, by the second processor, a thread to the linked list, wherein the thread is added to the monitored memory address.
20 . The method of claim 17 , further comprising:
determining, by a second processor, that the linked list is empty; and
adding an additional thread to the linked list and sending an interrupt to the processor.