IP Library Granted Patent US 7,982,547
Granted Patent B2
US 7,982,547 · App. 12/414,575 · Granted Jul 19, 2011

Phase locked loop-based tuning adjustable filter

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Quick Facts
Patent No.
US 7,982,547
App. No.
12/414,575
Granted
Jul 19, 2011
Kind
B2
Abstract

Phase locked loop based frequency tuning of an adjustable filter is disclosed. A resonant circuit includes the adjustable filter, and an oscillator signal provides an input to the resonant circuit.

Claims (51)

1. A system comprising:

a resonant circuit including an amplifier and an adjustable filter;

a phase locked loop (PLL) circuit incorporating the resonant circuit and configured to adjust the adjustable filter; and

a local oscillator configured to provide:

an oscillator signal for use in down converting signals, and

an input signal into the resonant circuit.

2. The system as recited in claim 1 , wherein:

the PLL circuit comprises a phase detector to detect a phase difference between the signal input into the resonant circuit and a signal output by the resonant circuit, and

the PLL circuit is configured to adjust the adjustable filter based on the phase difference.

3. The system as recited in claim 2 , wherein the PLL circuit further comprises a phase adjustment component to adjust the adjustable filter based on a phase offset characteristic of the amplifier or of the resonant circuit.

4. The system as recited in claim 2 , wherein the adjustable filter is adjusted by tuning the adjustable filter to a frequency.

5. The system as recited in claim 2 further comprising setting and storing an adjustment value for the adjustable filter, the adjustable filter configured to operate using the adjustment value.

6. A method comprising:

detecting a phase difference between a signal input into a circuit by a local oscillator and a signal output by the circuit, the circuit including an amplifier and an adjustable filter;

generating a phase difference signal that indicates the phase difference between a center frequency of the signal input into the circuit and a center frequency of the signal output by the circuit;

processing the phase difference signal to provide a tuning signal;

setting an adjustable characteristic of the adjustable filter using the tuning signal; and

down converting the signal output by the circuit using the signal input into the circuit by the local oscillator.

7. The method of claim 6 , wherein the acts of detecting, generating, processing and setting are performed using a circuit configuration approximating a phase locked loop (PLL).

8. The method of claim 6 , wherein processing the phase difference signal comprises:

adjusting the phase difference signal to accommodate a phase desired value.

9. The method of claim 6 further comprising

retaining a fixed adjustment value for the adjustable filter after one or more predetermined criteria have been met.

10. The method of claim 9 , wherein the one or more predetermined criteria are based upon a predetermined time elapsing after the signal input into the circuit is initially input into the circuit.

11. A method comprising:

providing an oscillation signal from a local oscillator to a first circuit and to a parallel coupled second circuit, the first circuit including an adjustable filter;

detecting a phase difference between a first output oscillation signal from the first circuit and a second output oscillation signal from the second circuit;

generating a phase difference signal indicating the phase difference between the first output oscillation signal and the second output oscillation signal;

filtering the phase difference signal using a low pass filter to generate a tuning signal having an adjustment value corresponding to the phase difference between the first output oscillation signal and the second output oscillation signal;

setting the adjustable filter based on the adjustment value of the tuning signal; and

when one or more predetermined criteria are met, the method further comprises:

disconnecting the oscillation signal from the first circuit and from the parallel coupled second circuit;

disconnecting the phase difference signal from the low pass filter; and

retaining an adjustment value of the adjustable filter at a fixed value after disconnecting the phase difference signal from the low pass filter.

12. The method of claim 11 , wherein the one or more predetermined criteria are based upon a predetermined time elapsing after the oscillation signal is initially provided to the first circuit.

13. The method of claim 11 further comprising modifying the adjustment value to compensate for a changed operating condition of the adjustable filter or the first circuit.

14. The method of claim 11 further comprising processing an incoming signal from an antenna using the first circuit, the adjustable filter having a fixed value based upon the retained adjustment value.

15. A system comprising:

a first circuit including an amplifier and an adjustable filter, the first circuit configured to receive an oscillator signal;

a second circuit coupled in parallel with the first circuit to receive the oscillator signal, the second circuit including an amplifier and a fixed value filter;

an adjustment circuit including a phase detector to detect a phase difference between an output oscillation signal from the first circuit and an output oscillation signal from the second circuit, the adjustment circuit configured as a phase locked loop (PLL) to generate a tuning signal to set an adjustment value of the first circuit based on the detected phase difference and to lock a center frequency of the first circuit to a frequency of the oscillator signal;

a first switch to selectively disconnect the oscillation signal from both the first circuit and the parallel coupled second circuit; and

a second switch to disconnect and disable the adjustment circuit from generating a tuning signal based on the detected phase difference,

wherein the adjustment circuit comprises a register circuit to retain the adjustment value during operation of the adjustable filter of the first circuit.

16. The system according to claim 15 , wherein the phase detector comprises a time to digital converter circuit to detect temporal spacing between an edge of the output oscillation signal from the first circuit and an edge of the output oscillation signal from the second circuit.

17. The system according to claim 15 ,

wherein the first switch is configured to periodically disconnect the oscillation signal for a predetermined period of time corresponding to a maximum transient recovery time of the first circuit.

18. The system according to claim 15 further comprising:

a third switch to connect an RF signal to the first circuit when the first and second switch are disconnected;

a compensator to periodically change the adjustment value to compensate for changed operating conditions of the first circuit; and

a down conversion and filtering component to receive and decode a filtered RF output signal from the first circuit using the oscillation signal.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2012
From: INFINEON TECHNOLOGIES AG
To: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
Reel/Frame 027548/0623 →