Apparatus and method for implementing instruction support for the data encryption standard (DES) algorithm

1. A processor, comprising:

an instruction fetch unit configured to issue instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA); and

a cryptographic unit configured to receive instructions for execution from the instruction fetch unit, wherein the instructions include one or more Data Encryption Standard (DES) instructions defined within said ISA, wherein each of the one or more DES instructions includes opcode bits and is executable by the cryptographic unit to implement a portion of a DES cipher that is compliant with Federal Information Processing Standards (FIPS) Publication 46-3, wherein an opcode encoded in the opcode bits of the given DES instruction is sufficient when executed to implement the portion of the DES cipher;

wherein in response to receiving a DES key expansion instruction defined within said ISA, the cryptographic unit is further configured to generate one or more of an intermediate set of values from an input key according to the DES cipher, wherein each given member of the intermediate set of values is generated such that upon application of a Permuted Choice 2 (PC 2 ) function of the DES cipher to any given member of the intermediate set, a corresponding expanded cipher key of the DES cipher key schedule is generated.

2. The processor as recited in claim 1 , wherein to generate the one or more of the intermediate set of values, the cryptographic unit is further configured to perform a bit rotation of an input operand specified by the DES key expansion instruction, wherein a number of bit positions of the bit rotation is indicated by a mode operand specified by the DES key expansion instruction.

3. The processor as recited in claim 1 , wherein to generate the one or more of the intermediate set of values, the cryptographic unit is further configured to selectively perform a bit rotation of an input operand specified by the DES key expansion instruction by 1, 2, or 4 bit positions, wherein the number of bit positions is selected dependent upon a mode operand specified by the DES key expansion instruction.

4. The processor as recited in claim 1 , wherein in response to receiving a DES initial permutation instruction defined within said ISA, the cryptographic unit is further configured to perform an initial permutation operation as defined by the DES cipher on an input operand specified by the DES initial permutation instruction.

5. The processor as recited in claim 1 , wherein in response to receiving a DES inverse initial permutation instruction defined within said ISA, the cryptographic unit is further configured to perform an inverse initial permutation operation as defined by the DES cipher on an input operand specified by the DES inverse initial permutation instruction.

6. The processor as recited in claim 1 , wherein in response to receiving a DES round instruction defined within said ISA, the cryptographic unit is further configured to perform one or more rounds of the DES cipher on a data input operand specified by the DES round instruction.

7. The processor as recited in claim 6 , wherein to perform the one or more rounds of the DES cipher, the cryptographic unit is further configured to generate one or more expanded cipher keys of the DES cipher key schedule by applying the PC 2 function of the DES cipher to one or more intermediate-value input operands specified by the DES round instruction.

8. The processor as recited in claim 1 , wherein in response to receiving a DES round instruction defined within said ISA, the cryptographic unit is further configured to perform two rounds of the DES cipher on the data input operand and to generate a result value indicative of the result of the second of the two rounds of the DES cipher that are performed.

9. The processor as recited in claim 1 , wherein the ISA is compliant with one or more of IEEE 1754-1994 (SPARC Version 8), SPARC Version 9, UltraSPARC Architecture 2005, or UltraSPARC Architecture 2009.

10. A system, comprising:

a system memory, and

the processor as recited in claim 1 coupled to the system memory.

11. A method, comprising:

a hardware processor issuing instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA);

a hardware cryptographic unit of the processor receiving ones of said instructions for execution, wherein the instructions include one or more Data Encryption Standard (DES) instructions defined within said ISA, wherein each of the one or more DES instructions includes opcode bits and is executable by the cryptographic unit to implement a portion of a DES cipher that is compliant with Federal Information Processing Standards (FIPS) Publication 46-3, wherein an opcode encoded in the opcode bits of the given DES instruction is sufficient when executed to implement the portion of the DES cipher; and

in response to receiving a DES key expansion instruction defined within said ISA, the hardware cryptographic unit generating one or more of an intermediate set of values from an input key according to the DES cipher, wherein each given member of the intermediate set of values is generated such that upon application of a Permuted Choice 2 (PC 2 ) function of the DES cipher to any given member of the intermediate set, a corresponding expanded cipher key of the DES cipher key schedule is generated.

12. The method as recited in claim 11 , wherein generating the one or more of the intermediate set of values comprises the hardware cryptographic unit performing a bit rotation of an input operand specified by the DES key expansion instruction by a number of bit positions that is indicated by a mode operand specified by the DES key expansion instruction.

13. The method as recited in claim 11 , wherein generating the one or more of the intermediate set of values comprises the hardware cryptographic unit selectively performing a bit rotation of an input operand specified by the DES key expansion instruction by 1, 2, or 4 bit positions, wherein the number of bit positions is selected dependent upon a mode operand specified by the DES key expansion instruction.

14. The method as recited in claim 11 , further comprising:

in response to receiving a DES initial permutation instruction defined within said ISA, the hardware cryptographic unit performing an initial permutation operation as defined by the DES cipher on an input operand specified by the DES initial permutation instruction.

15. The method as recited in claim 11 , further comprising:

in response to receiving a DES inverse initial permutation instruction defined within said ISA, the hardware cryptographic unit performing an inverse initial permutation operation as defined by the DES cipher on an input operand specified by the DES inverse initial permutation instruction.

16. The method as recited in claim 11 , further comprising:

in response to receiving a DES round instruction defined within said ISA, the hardware cryptographic unit performing one or more rounds of the DES cipher on a data input operand specified by the DES round instruction.

17. The method as recited in claim 16 , wherein performing the one or more rounds of the DES cipher comprises the hardware cryptographic unit generating one or more expanded cipher keys of the DES cipher key schedule by applying the PC 2 function of the DES cipher to one or more intermediate-value input operands specified by the DES round instruction.

18. The method as recited in claim 11 , further comprising:

in response to receiving a DES round instruction defined within said ISA, the hardware cryptographic unit performing two rounds of the DES cipher on the data input operand and generating a result value indicative of the result of the second of the two rounds of the DES cipher that are performed.

19. The method as recited in claim 11 , wherein the ISA is compliant with one or more of IEEE 1754-1994 (SPARC Version 8), SPARC Version 9, UltraSPARC Architecture 2005, or UltraSPARC Architecture 2009.

20. A processor, comprising:

an instruction fetch unit configured to issue instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA); and

a cryptographic unit configured to receive instructions for execution from the instruction fetch unit, wherein the instructions include one or more Data Encryption Standard (DES) instructions defined within said ISA, wherein each of the one or more DES instructions includes opcode bits and is executable by the cryptographic unit to implement a portion of a DES cipher that is compliant with Federal Information Processing Standards (FIPS) Publication 46-3, wherein an opcode encoded in the opcode bits of the given DES instruction is sufficient when executed to implement the portion of the DES cipher;

wherein in response to receiving a DES key expansion instruction defined within said ISA, the cryptographic unit is further configured to generate one or more expanded cipher keys of the DES cipher key schedule from an input key.

21. The processor as recited in claim 20 , wherein to generate the one or more expanded cipher keys, the cryptographic unit is further configured to perform a bit rotation of an input operand specified by the DES key expansion instruction, wherein a number of bit positions of the bit rotation is indicated by a mode operand specified by the DES key expansion instruction.

22. The processor as recited in claim 20 , wherein to generate the one or more of the expanded cipher keys, the cryptographic unit is further configured to selectively perform a bit rotation of an input operand specified by the DES key expansion instruction by 1, 2, or 4 bit positions, wherein the number of bit positions is selected dependent upon a mode operand specified by the DES key expansion instruction.

23. A method, comprising:

a hardware processor issuing instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA);

a hardware cryptographic unit of the processor receiving ones of said instructions for execution, wherein the instructions include one or more Data Encryption Standard (DES) instructions defined within said ISA, wherein each of the one or more DES instructions includes opcode bits and is executable by the cryptographic unit to implement a portion of a DES cipher that is compliant with Federal Information Processing Standards (FIPS) Publication 46-3, wherein an opcode encoded in the opcode bits of the given DES instruction is sufficient when executed to implement the portion of the DES cipher; and

in response to receiving a DES key expansion instruction defined within said ISA, the hardware cryptographic unit generating one or more expanded cipher keys of the DES cipher key schedule from an input key.

24. The method as recited in claim 23 , wherein generating the one or more of the expanded cipher keys comprises the hardware cryptographic unit performing a bit rotation of an input operand specified by the DES key expansion instruction by a number of bit positions that is indicated by a mode operand specified by the DES key expansion instruction.

25. The method as recited in claim 23 , wherein generating the one or more of the expanded cipher keys comprises the hardware cryptographic unit selectively performing a bit rotation of an input operand specified by the DES key expansion instruction by 1, 2, or 4 bit positions, wherein the number of bit positions is selected dependent upon a mode operand specified by the DES key expansion instruction.