Double heterojunction bipolar transistor having graded base region

1 . A semiconductor device comprising a heterojunction, comprising:

a first region comprising a first III-V semiconductor;

a second region adjacent to the first region and comprising a second III-V semiconductor material, wherein the second III-V semiconductor material comprises a material of graded concentration over a width of the second region; and

a third region adjacent to the second region and comprising a third III-V semiconductor material, wherein the graded concentration is selection to provide substantially no conduction band discontinuity at a junction of the second region and the third region, or to provide a type I semiconductor junction at the junction of the second region and the third region.

2 . A semiconductor device as claimed in claim 1 , wherein the first III-V semiconductor is substantially lattice-matched to the second III-V semiconductor.

3 . A semiconductor device as claimed in claim 1 , wherein the second III-V semiconductor is substantially lattice matched to the third III-V semiconductor.

4 . A semiconductor device as claimed in claim 1 , wherein the material of graded concentration comprises a minimum concentration at junction of the first III-V semiconductor and the second III-V semiconductor.

5 . A semiconductor device as claimed in claim 1 , wherein the material of graded concentration comprises a maximum concentration at junction of the second III-V semiconductor and the third III-V semiconductor.

6 . A semiconductor device as claimed in claim 1 , wherein the second III-V semiconductor comprises a bandgap energy that increases across the second region between a junction of the first region and the second region and the junction of the second region and the third region.

7 . A semiconductor device as claimed in claim 6 , wherein a conduction band level increases across the second region between a junction of the first region and the second region and the junction of the second region and the third region.

8 . A double heterojunction bipolar transistor (DHBT), comprising:

a first region comprising a first III-V semiconductor;

a second region forming a first heterojunction with the first region and comprising Al x Ga 1-x AsSb wherein the concentration of Al is graded concentration over a width of the second region; and

a third region forming a second heterojunction with the second region and comprising a second III-V semiconductor, wherein the graded concentration is selection to provide substantially no conduction band discontinuity at a junction of the second region and the third region, or to provide a type I semiconductor junction at the junction of the second region and the third region.

9 . A DHBT as claimed in claim 8 , wherein x is approximately zero at the first heterojunction and x is less than approximately 0.20 at the second heterojunction.

10 . A DHBT as claimed in claim 8 , wherein x is approximately zero at the first heterojunction and x is less than or equal to approximately 0.17 at the second heterojunction.

11 . A DHBT as claimed in claim 8 , wherein x is approximately zero at the first heterojunction and x is approximately 0.09 at the second heterojunction.

12 . A DHBT as claimed in claim 8 , wherein the first III-V semiconductor comprises InP.

13 . A DHBT as claimed in claim 8 , wherein the third III-V semiconductor comprises AlInAs.

14 . A DHBT as claimed in claim 13 , wherein the AlInAs is substantially lattice-matched to a layer of InP.

15 . A DHBT as claimed in claim 8 , wherein the second III-V semiconductor comprises a bandgap energy that increases across the second region between the first heterojunction and the second heterojunction.

16 . A DHBT as claimed in claim 15 , wherein a conduction band level increases across the second region between the first heterojunction and the second heterojunction.