Lock detection circuit for phase locked loop
A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal.
1. A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal, comprising:
a first counter that outputs a first counter value indicative of a number of clock cycles of the reference signal;
a second counter that outputs a second counter value indicative of a number of clock cycles of the feedback signal;
an asynchronous comparator connected to the first and second counters and receives the first and second counter values and generates a comparator output signal having a pulse width that is proportional to the difference between the first and second counter values;
a pulse width detector, connected to the comparator, that receives the comparator output signal and generates an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value; and
a state machine, connected to the pulse width detector, for controlling the state of at least one lock indication signal according to the pulse width detector output signal,
wherein when the pulse width detector output signal indicates that the pulse width of the comparator output signal exceeds the predetermined threshold value, the state machine asynchronously resets the first and second counters, and wherein the first and second counters continue to increment otherwise.
2. The lock detector circuit of claim 1 , wherein the pulse width detector output signal is indicative of the pulse width of the comparators output signal exceeding the predetermined threshold value.
3. The lock detector circuit of claim 2 , wherein the predetermined threshold value is settable and/or adjustable.
4. The lock detector circuit of claim 2 , further comprising:
a third counter for conducting a count sequence while the pulse width detector output signal is indicative of the comparator output signal not exceeding the predetermined threshold value, and wherein when the third counter count sequence value equals or exceeds a predetermined count value, the state machine controls the lock indication signal to indicate a lock condition.
5. The lock detector circuit of claim 1 , wherein when the pulse width detector output signal indicates that the pulse width of the comparator output signal exceeds the predetermined threshold value, the state machine asynchronously controls the lock indication signal to indicate an out of lock condition.
6. The lock detector circuit of claim 1 , wherein the comparator compares the first and second counter values at each active edge of the reference clock signal and the feedback clock signal.
7. A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal, comprising:
a first counter outputting a first counter value indicative of a number of clock cycles of the reference signal;
a second counter outputting a second counter value indicative of a number of clock cycles of the feedback signal;
an asynchronous comparator that receives the first and second counter values and generates a comparator output signal having a pulse width that is proportional to the difference between the first and second counter values;
a pulse width detector that receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value; and
a state machine that receives the pulse width detector output signal and:
when the pulse width detector output signal is indicative of the comparator output signal exceeding the predetermined threshold value, asynchronously resetting the first and second counters and providing a lock indication signal indicative of an out of lock condition, and
when the pulse width detector output signal is indicative of the comparator output signal not exceeding the predetermined threshold value, and after detecting a predetermined number of consecutive increments of the first and second counters, providing a lock indication signal indicative of a lock condition.
8. The lock detector circuit of claim 7 , wherein the predetermined threshold value is settable and/or adjustable.
9. The lock detector circuit of claim 8 , wherein the comparator compares the first and second counter values at each active edge of the reference clock signal and the feedback signal.
10. A method of detecting a lock condition between a reference signal and a feedback signal, comprising:
providing a first counter that outputs a first counter value indicative of a number of clock cycles of the reference signal;
providing a second counter that outputs a second counter value indicative of a number of clock cycles of the feedback signal;
comparing the first counter value and the second counter value and producing a first signal having a pulse width that is proportional to the difference between the first and second counter values;
detecting the pulse width of the first signal and producing a second signal that is indicative of the relationship between the pulse width of the first signal and a predetermined threshold value;
controlling the state of at least one lock indication signal according to the second signal;
when the second signal is indicative of the first signal exceeding the predetermined threshold value, asynchronously resetting the first and second counters and providing a lock indication signal indicative of an out of lock condition; and
when the second signal is indicative of the first signal not exceeding the predetermined threshold value, and after detecting a predetermined number of consecutive increments of the first and second counters, providing a lock indication signal indicative of a lock condition.
11. The method of detecting a lock condition of claim 10 , wherein the predetermined threshold value is settable and/or adjustable.
12. The method of detecting a lock condition of claim 10 , wherein the comparison is conducted at each active edge of the reference clock signal and the feedback clock signal.