Low-complexity digital radio interface
View Patent ↗A radio integrated circuit includes, in part, an analog front end block, an analog-to-digital converter responsive to the analog-front end block, a digital signal processor responsive to the analog-to-digital converter and adapted to generate in-phase and quadrature signals, and a serial communication interface configured to receive and transmit the in-phase and quadrature signals. The serial communication interface supplies a gain control signal to the analog front end block when a switch disposed in the radio integrated circuit is in a first position. When the switch is in a second position, a gain control block disposed in the radio integrated circuit receives a gain control signal from the analog-to-digital converter and supplies the gain control signal to the analog front end block. The digital signal processor may be configured to interleave the in-phase and quadrature signals.
1. A tuner comprising:
an analog front end block;
an analog-to-digital converter responsive to the analog-front end block;
a digital signal processor responsive to said analog-to-digital converter and adapted to output in-phase and quadrature data via a first terminal, wherein said digital signal processor is further configured to interleave the in-phase and quadrature data, said first terminal carrying a first subset of bits associated with the in-phase and quadrature data;
a serial communication interface block receiving a first gain control signal via a second terminal, said serial communication interface block being further configured to supply the first gain control signal to the analog front end block when a switch is in a first position;
a gain control block adapted to receive a second gain control signal from the analog-to-digital converter and to supply the second gain control signal to the analog front end block when the switch is in a second position; and
a third terminal carrying a second subset of bits associated with the in-phase and quadrature signals, said first and second subsets representing an entire set of bits associated with the in-phase and quadrature data, wherein the first subset of bits associated with the in-phase and quadrature data is transmitted in a first data packet having a synchronization header, and the second subset of bits associated with the in-phase and quadrature data is transmitted in a second data packet, the first and second data packets sharing a same clock signal.
2. The tuner of claim 1 wherein said digital signal processor is further configured to insert synchronization bits between bits of the interleave in-phase and quadrature data.
3. The tuner of claim 1 wherein the in-phase and quadrature data are in a 2's complement form.
4. The tuner of claim 1 wherein the interleaved in-phase and quadrature data are transmitted in a data packet having a synchronization pattern.
5. The tuner of claim 4 wherein the synchronization pattern comprises a single bit.
6. The tuner of claim 1 wherein the second data packet carries auxiliary data in additional to the second subset of bits associated with the in-phase and quadrature data.
7. A method of processing communication signals, the method comprising:
amplifying a received analog signal;
converting the amplified analog signal to a digital signal;
processing the digital signal to generate in-phase and quadrature data;
transmitting the in-phase and quadrature data via a first terminal;
receiving a first gain control signal via a serial communication interface;
varying an amplitude of the analog signal in accordance with the first gain control signal when a switch is in a first position;
varying an amplification level of the analog signal in accordance with the second gain control signal when the switch is in a second position, said second gain control signal being representative of the converted digital signal;
transmitting a first subset of the in-phase and quadrature data via the first terminal; and
transmitting a second subset of the in-phase and quadrature data via a second terminal, said first and second subsets representing an entire set of bits associated with the in-phase and quadrature signals, wherein the first subset of the in-phase and quadrature data is transmitted in a first data packet having a synchronization pattern, and the second subset of the in-phase and quadrature data is transmitted in a second data packet, the first and second data packets sharing a same clock signal.
8. The method of claim 7 further comprising:
interleaving the in-phase and quadrature data.
9. The method of claim 8 further comprising:
inserting synchronization bits between bits of the interleaved in-phase and quadrature data.
10. The method of claim 7 further comprising:
receiving a command via the serial communication interface; and
setting a plurality of bits of the in-phase and quadrature data to a logical binary value in response to the received command.
11. The method of claim 7 wherein the in-phase and quadrature data are in a 2's complement form.
12. The method of claim 7 wherein the synchronization pattern comprises a single bit.
13. The method of claim 7 wherein the second data packet comprises auxiliary data in addition to the second subset of the in-phase and quadrature data.